eos_s3/ext_regs_ffe/
csr.rs

1#[doc = "Register `CSR` reader"]
2pub struct R(crate::R<CSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CSR` writer"]
17pub struct W(crate::W<CSR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CSR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CSR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CSR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `wb_ms_start` reader - Wishbone master start transactions. This bit is self clearing."]
38pub struct WB_MS_START_R(crate::FieldReader<bool, bool>);
39impl WB_MS_START_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: bool) -> Self {
42        WB_MS_START_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for WB_MS_START_R {
46    type Target = crate::FieldReader<bool, bool>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `wb_ms_start` writer - Wishbone master start transactions. This bit is self clearing."]
53pub struct WB_MS_START_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> WB_MS_START_W<'a> {
57    #[doc = r"Sets the field bit"]
58    #[inline(always)]
59    pub fn set_bit(self) -> &'a mut W {
60        self.bit(true)
61    }
62    #[doc = r"Clears the field bit"]
63    #[inline(always)]
64    pub fn clear_bit(self) -> &'a mut W {
65        self.bit(false)
66    }
67    #[doc = r"Writes raw bits to the field"]
68    #[inline(always)]
69    pub fn bit(self, value: bool) -> &'a mut W {
70        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
71        self.w
72    }
73}
74#[doc = "Wishbone master write enable.\n\nValue on reset: 0"]
75#[derive(Clone, Copy, Debug, PartialEq)]
76pub enum WB_MS_WEN_A {
77    #[doc = "0: read"]
78    READ = 0,
79    #[doc = "1: write"]
80    WRITE = 1,
81}
82impl From<WB_MS_WEN_A> for bool {
83    #[inline(always)]
84    fn from(variant: WB_MS_WEN_A) -> Self {
85        variant as u8 != 0
86    }
87}
88#[doc = "Field `wb_ms_wen` reader - Wishbone master write enable."]
89pub struct WB_MS_WEN_R(crate::FieldReader<bool, WB_MS_WEN_A>);
90impl WB_MS_WEN_R {
91    #[inline(always)]
92    pub(crate) fn new(bits: bool) -> Self {
93        WB_MS_WEN_R(crate::FieldReader::new(bits))
94    }
95    #[doc = r"Get enumerated values variant"]
96    #[inline(always)]
97    pub fn variant(&self) -> WB_MS_WEN_A {
98        match self.bits {
99            false => WB_MS_WEN_A::READ,
100            true => WB_MS_WEN_A::WRITE,
101        }
102    }
103    #[doc = "Checks if the value of the field is `READ`"]
104    #[inline(always)]
105    pub fn is_read(&self) -> bool {
106        **self == WB_MS_WEN_A::READ
107    }
108    #[doc = "Checks if the value of the field is `WRITE`"]
109    #[inline(always)]
110    pub fn is_write(&self) -> bool {
111        **self == WB_MS_WEN_A::WRITE
112    }
113}
114impl core::ops::Deref for WB_MS_WEN_R {
115    type Target = crate::FieldReader<bool, WB_MS_WEN_A>;
116    #[inline(always)]
117    fn deref(&self) -> &Self::Target {
118        &self.0
119    }
120}
121#[doc = "Field `wb_ms_wen` writer - Wishbone master write enable."]
122pub struct WB_MS_WEN_W<'a> {
123    w: &'a mut W,
124}
125impl<'a> WB_MS_WEN_W<'a> {
126    #[doc = r"Writes `variant` to the field"]
127    #[inline(always)]
128    pub fn variant(self, variant: WB_MS_WEN_A) -> &'a mut W {
129        self.bit(variant.into())
130    }
131    #[doc = "read"]
132    #[inline(always)]
133    pub fn read(self) -> &'a mut W {
134        self.variant(WB_MS_WEN_A::READ)
135    }
136    #[doc = "write"]
137    #[inline(always)]
138    pub fn write(self) -> &'a mut W {
139        self.variant(WB_MS_WEN_A::WRITE)
140    }
141    #[doc = r"Sets the field bit"]
142    #[inline(always)]
143    pub fn set_bit(self) -> &'a mut W {
144        self.bit(true)
145    }
146    #[doc = r"Clears the field bit"]
147    #[inline(always)]
148    pub fn clear_bit(self) -> &'a mut W {
149        self.bit(false)
150    }
151    #[doc = r"Writes raw bits to the field"]
152    #[inline(always)]
153    pub fn bit(self, value: bool) -> &'a mut W {
154        self.w.bits =
155            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
156        self.w
157    }
158}
159#[doc = "Mux select between SM and WB masters.\n\nValue on reset: 0"]
160#[derive(Clone, Copy, Debug, PartialEq)]
161pub enum MUX_WB_SM_AW {
162    #[doc = "0: Select SM WB Master."]
163    SM_WISHBONE_MASTER = 0,
164    #[doc = "1: Select WB Master."]
165    WISHBONE_MASTER = 1,
166}
167impl From<MUX_WB_SM_AW> for bool {
168    #[inline(always)]
169    fn from(variant: MUX_WB_SM_AW) -> Self {
170        variant as u8 != 0
171    }
172}
173#[doc = "Field `mux_wb_sm` writer - Mux select between SM and WB masters."]
174pub struct MUX_WB_SM_W<'a> {
175    w: &'a mut W,
176}
177impl<'a> MUX_WB_SM_W<'a> {
178    #[doc = r"Writes `variant` to the field"]
179    #[inline(always)]
180    pub fn variant(self, variant: MUX_WB_SM_AW) -> &'a mut W {
181        self.bit(variant.into())
182    }
183    #[doc = "Select SM WB Master."]
184    #[inline(always)]
185    pub fn sm_wishbone_master(self) -> &'a mut W {
186        self.variant(MUX_WB_SM_AW::SM_WISHBONE_MASTER)
187    }
188    #[doc = "Select WB Master."]
189    #[inline(always)]
190    pub fn wishbone_master(self) -> &'a mut W {
191        self.variant(MUX_WB_SM_AW::WISHBONE_MASTER)
192    }
193    #[doc = r"Sets the field bit"]
194    #[inline(always)]
195    pub fn set_bit(self) -> &'a mut W {
196        self.bit(true)
197    }
198    #[doc = r"Clears the field bit"]
199    #[inline(always)]
200    pub fn clear_bit(self) -> &'a mut W {
201        self.bit(false)
202    }
203    #[doc = r"Writes raw bits to the field"]
204    #[inline(always)]
205    pub fn bit(self, value: bool) -> &'a mut W {
206        self.w.bits =
207            (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
208        self.w
209    }
210}
211#[doc = "Field `BUSY` reader - Indicates if the Wishbone is busy"]
212pub struct BUSY_R(crate::FieldReader<bool, bool>);
213impl BUSY_R {
214    #[inline(always)]
215    pub(crate) fn new(bits: bool) -> Self {
216        BUSY_R(crate::FieldReader::new(bits))
217    }
218}
219impl core::ops::Deref for BUSY_R {
220    type Target = crate::FieldReader<bool, bool>;
221    #[inline(always)]
222    fn deref(&self) -> &Self::Target {
223        &self.0
224    }
225}
226#[doc = "Field `OVFL` reader - Indicates if there's a FFE push operation overflow"]
227pub struct OVFL_R(crate::FieldReader<bool, bool>);
228impl OVFL_R {
229    #[inline(always)]
230    pub(crate) fn new(bits: bool) -> Self {
231        OVFL_R(crate::FieldReader::new(bits))
232    }
233}
234impl core::ops::Deref for OVFL_R {
235    type Target = crate::FieldReader<bool, bool>;
236    #[inline(always)]
237    fn deref(&self) -> &Self::Target {
238        &self.0
239    }
240}
241#[doc = "I2C_0 wishbone control mux select\n\nValue on reset: 0"]
242#[derive(Clone, Copy, Debug, PartialEq)]
243pub enum I2C0_MUX_SEL_A {
244    #[doc = "0: Let SM1 control the port."]
245    SM1_AS_CONTROLLER = 0,
246    #[doc = "1: Let Wishbone Master control the port"]
247    WB_MASTER_AS_CONTROLLER = 1,
248}
249impl From<I2C0_MUX_SEL_A> for bool {
250    #[inline(always)]
251    fn from(variant: I2C0_MUX_SEL_A) -> Self {
252        variant as u8 != 0
253    }
254}
255#[doc = "Field `i2c0_mux_sel` reader - I2C_0 wishbone control mux select"]
256pub struct I2C0_MUX_SEL_R(crate::FieldReader<bool, I2C0_MUX_SEL_A>);
257impl I2C0_MUX_SEL_R {
258    #[inline(always)]
259    pub(crate) fn new(bits: bool) -> Self {
260        I2C0_MUX_SEL_R(crate::FieldReader::new(bits))
261    }
262    #[doc = r"Get enumerated values variant"]
263    #[inline(always)]
264    pub fn variant(&self) -> I2C0_MUX_SEL_A {
265        match self.bits {
266            false => I2C0_MUX_SEL_A::SM1_AS_CONTROLLER,
267            true => I2C0_MUX_SEL_A::WB_MASTER_AS_CONTROLLER,
268        }
269    }
270    #[doc = "Checks if the value of the field is `SM1_AS_CONTROLLER`"]
271    #[inline(always)]
272    pub fn is_sm1_as_controller(&self) -> bool {
273        **self == I2C0_MUX_SEL_A::SM1_AS_CONTROLLER
274    }
275    #[doc = "Checks if the value of the field is `WB_MASTER_AS_CONTROLLER`"]
276    #[inline(always)]
277    pub fn is_wb_master_as_controller(&self) -> bool {
278        **self == I2C0_MUX_SEL_A::WB_MASTER_AS_CONTROLLER
279    }
280}
281impl core::ops::Deref for I2C0_MUX_SEL_R {
282    type Target = crate::FieldReader<bool, I2C0_MUX_SEL_A>;
283    #[inline(always)]
284    fn deref(&self) -> &Self::Target {
285        &self.0
286    }
287}
288#[doc = "Field `i2c0_mux_sel` writer - I2C_0 wishbone control mux select"]
289pub struct I2C0_MUX_SEL_W<'a> {
290    w: &'a mut W,
291}
292impl<'a> I2C0_MUX_SEL_W<'a> {
293    #[doc = r"Writes `variant` to the field"]
294    #[inline(always)]
295    pub fn variant(self, variant: I2C0_MUX_SEL_A) -> &'a mut W {
296        self.bit(variant.into())
297    }
298    #[doc = "Let SM1 control the port."]
299    #[inline(always)]
300    pub fn sm1_as_controller(self) -> &'a mut W {
301        self.variant(I2C0_MUX_SEL_A::SM1_AS_CONTROLLER)
302    }
303    #[doc = "Let Wishbone Master control the port"]
304    #[inline(always)]
305    pub fn wb_master_as_controller(self) -> &'a mut W {
306        self.variant(I2C0_MUX_SEL_A::WB_MASTER_AS_CONTROLLER)
307    }
308    #[doc = r"Sets the field bit"]
309    #[inline(always)]
310    pub fn set_bit(self) -> &'a mut W {
311        self.bit(true)
312    }
313    #[doc = r"Clears the field bit"]
314    #[inline(always)]
315    pub fn clear_bit(self) -> &'a mut W {
316        self.bit(false)
317    }
318    #[doc = r"Writes raw bits to the field"]
319    #[inline(always)]
320    pub fn bit(self, value: bool) -> &'a mut W {
321        self.w.bits =
322            (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
323        self.w
324    }
325}
326#[doc = "I2C_1 wishbone control mux select"]
327pub type I2C1_MUX_SEL_A = I2C0_MUX_SEL_A;
328#[doc = "Field `i2c1_mux_sel` reader - I2C_1 wishbone control mux select"]
329pub type I2C1_MUX_SEL_R = I2C0_MUX_SEL_R;
330#[doc = "Field `i2c1_mux_sel` writer - I2C_1 wishbone control mux select"]
331pub struct I2C1_MUX_SEL_W<'a> {
332    w: &'a mut W,
333}
334impl<'a> I2C1_MUX_SEL_W<'a> {
335    #[doc = r"Writes `variant` to the field"]
336    #[inline(always)]
337    pub fn variant(self, variant: I2C1_MUX_SEL_A) -> &'a mut W {
338        self.bit(variant.into())
339    }
340    #[doc = "Let SM1 control the port."]
341    #[inline(always)]
342    pub fn sm1_as_controller(self) -> &'a mut W {
343        self.variant(I2C1_MUX_SEL_A::SM1_AS_CONTROLLER)
344    }
345    #[doc = "Let Wishbone Master control the port"]
346    #[inline(always)]
347    pub fn wb_master_as_controller(self) -> &'a mut W {
348        self.variant(I2C1_MUX_SEL_A::WB_MASTER_AS_CONTROLLER)
349    }
350    #[doc = r"Sets the field bit"]
351    #[inline(always)]
352    pub fn set_bit(self) -> &'a mut W {
353        self.bit(true)
354    }
355    #[doc = r"Clears the field bit"]
356    #[inline(always)]
357    pub fn clear_bit(self) -> &'a mut W {
358        self.bit(false)
359    }
360    #[doc = r"Writes raw bits to the field"]
361    #[inline(always)]
362    pub fn bit(self, value: bool) -> &'a mut W {
363        self.w.bits =
364            (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
365        self.w
366    }
367}
368#[doc = "spi_0 wishbone control mux select"]
369pub type SPI0_MUX_SEL_A = I2C0_MUX_SEL_A;
370#[doc = "Field `spi0_mux_sel` reader - spi_0 wishbone control mux select"]
371pub type SPI0_MUX_SEL_R = I2C0_MUX_SEL_R;
372#[doc = "Field `spi0_mux_sel` writer - spi_0 wishbone control mux select"]
373pub struct SPI0_MUX_SEL_W<'a> {
374    w: &'a mut W,
375}
376impl<'a> SPI0_MUX_SEL_W<'a> {
377    #[doc = r"Writes `variant` to the field"]
378    #[inline(always)]
379    pub fn variant(self, variant: SPI0_MUX_SEL_A) -> &'a mut W {
380        self.bit(variant.into())
381    }
382    #[doc = "Let SM1 control the port."]
383    #[inline(always)]
384    pub fn sm1_as_controller(self) -> &'a mut W {
385        self.variant(SPI0_MUX_SEL_A::SM1_AS_CONTROLLER)
386    }
387    #[doc = "Let Wishbone Master control the port"]
388    #[inline(always)]
389    pub fn wb_master_as_controller(self) -> &'a mut W {
390        self.variant(SPI0_MUX_SEL_A::WB_MASTER_AS_CONTROLLER)
391    }
392    #[doc = r"Sets the field bit"]
393    #[inline(always)]
394    pub fn set_bit(self) -> &'a mut W {
395        self.bit(true)
396    }
397    #[doc = r"Clears the field bit"]
398    #[inline(always)]
399    pub fn clear_bit(self) -> &'a mut W {
400        self.bit(false)
401    }
402    #[doc = r"Writes raw bits to the field"]
403    #[inline(always)]
404    pub fn bit(self, value: bool) -> &'a mut W {
405        self.w.bits =
406            (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
407        self.w
408    }
409}
410impl R {
411    #[doc = "Bit 0 - Wishbone master start transactions. This bit is self clearing."]
412    #[inline(always)]
413    pub fn wb_ms_start(&self) -> WB_MS_START_R {
414        WB_MS_START_R::new((self.bits & 0x01) != 0)
415    }
416    #[doc = "Bit 1 - Wishbone master write enable."]
417    #[inline(always)]
418    pub fn wb_ms_wen(&self) -> WB_MS_WEN_R {
419        WB_MS_WEN_R::new(((self.bits >> 1) & 0x01) != 0)
420    }
421    #[doc = "Bit 3 - Indicates if the Wishbone is busy"]
422    #[inline(always)]
423    pub fn busy(&self) -> BUSY_R {
424        BUSY_R::new(((self.bits >> 3) & 0x01) != 0)
425    }
426    #[doc = "Bit 4 - Indicates if there's a FFE push operation overflow"]
427    #[inline(always)]
428    pub fn ovfl(&self) -> OVFL_R {
429        OVFL_R::new(((self.bits >> 4) & 0x01) != 0)
430    }
431    #[doc = "Bit 5 - I2C_0 wishbone control mux select"]
432    #[inline(always)]
433    pub fn i2c0_mux_sel(&self) -> I2C0_MUX_SEL_R {
434        I2C0_MUX_SEL_R::new(((self.bits >> 5) & 0x01) != 0)
435    }
436    #[doc = "Bit 6 - I2C_1 wishbone control mux select"]
437    #[inline(always)]
438    pub fn i2c1_mux_sel(&self) -> I2C1_MUX_SEL_R {
439        I2C1_MUX_SEL_R::new(((self.bits >> 6) & 0x01) != 0)
440    }
441    #[doc = "Bit 7 - spi_0 wishbone control mux select"]
442    #[inline(always)]
443    pub fn spi0_mux_sel(&self) -> SPI0_MUX_SEL_R {
444        SPI0_MUX_SEL_R::new(((self.bits >> 7) & 0x01) != 0)
445    }
446}
447impl W {
448    #[doc = "Bit 0 - Wishbone master start transactions. This bit is self clearing."]
449    #[inline(always)]
450    pub fn wb_ms_start(&mut self) -> WB_MS_START_W {
451        WB_MS_START_W { w: self }
452    }
453    #[doc = "Bit 1 - Wishbone master write enable."]
454    #[inline(always)]
455    pub fn wb_ms_wen(&mut self) -> WB_MS_WEN_W {
456        WB_MS_WEN_W { w: self }
457    }
458    #[doc = "Bit 2 - Mux select between SM and WB masters."]
459    #[inline(always)]
460    pub fn mux_wb_sm(&mut self) -> MUX_WB_SM_W {
461        MUX_WB_SM_W { w: self }
462    }
463    #[doc = "Bit 5 - I2C_0 wishbone control mux select"]
464    #[inline(always)]
465    pub fn i2c0_mux_sel(&mut self) -> I2C0_MUX_SEL_W {
466        I2C0_MUX_SEL_W { w: self }
467    }
468    #[doc = "Bit 6 - I2C_1 wishbone control mux select"]
469    #[inline(always)]
470    pub fn i2c1_mux_sel(&mut self) -> I2C1_MUX_SEL_W {
471        I2C1_MUX_SEL_W { w: self }
472    }
473    #[doc = "Bit 7 - spi_0 wishbone control mux select"]
474    #[inline(always)]
475    pub fn spi0_mux_sel(&mut self) -> SPI0_MUX_SEL_W {
476        SPI0_MUX_SEL_W { w: self }
477    }
478    #[doc = "Writes raw bits to the register."]
479    #[inline(always)]
480    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
481        self.0.bits(bits);
482        self
483    }
484}
485#[doc = "Control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"]
486pub struct CSR_SPEC;
487impl crate::RegisterSpec for CSR_SPEC {
488    type Ux = u32;
489}
490#[doc = "`read()` method returns [csr::R](R) reader structure"]
491impl crate::Readable for CSR_SPEC {
492    type Reader = R;
493}
494#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"]
495impl crate::Writable for CSR_SPEC {
496    type Writer = W;
497}
498#[doc = "`reset()` method sets CSR to value 0"]
499impl crate::Resettable for CSR_SPEC {
500    #[inline(always)]
501    fn reset_value() -> Self::Ux {
502        0
503    }
504}
eos_s3/ext_regs_ffe/csr.rs

eos_s3/ext_regs_ffe/
csr.rs
