1#[doc = "Register `DMA_INTR` reader"]
2pub struct R(crate::R<DMA_INTR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DMA_INTR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DMA_INTR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DMA_INTR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Field `dma_herror` reader - 1: hresp=1, 0: hresp didn't go to 1, write one to clr"]
17pub struct DMA_HERROR_R(crate::FieldReader<bool, bool>);
18impl DMA_HERROR_R {
19 #[inline(always)]
20 pub(crate) fn new(bits: bool) -> Self {
21 DMA_HERROR_R(crate::FieldReader::new(bits))
22 }
23}
24impl core::ops::Deref for DMA_HERROR_R {
25 type Target = crate::FieldReader<bool, bool>;
26 #[inline(always)]
27 fn deref(&self) -> &Self::Target {
28 &self.0
29 }
30}
31#[doc = "Field `rx_data_available` reader - 1: rx threshold was hit, 0:threshold was not hit. This is before external mask bit."]
32pub struct RX_DATA_AVAILABLE_R(crate::FieldReader<bool, bool>);
33impl RX_DATA_AVAILABLE_R {
34 #[inline(always)]
35 pub(crate) fn new(bits: bool) -> Self {
36 RX_DATA_AVAILABLE_R(crate::FieldReader::new(bits))
37 }
38}
39impl core::ops::Deref for RX_DATA_AVAILABLE_R {
40 type Target = crate::FieldReader<bool, bool>;
41 #[inline(always)]
42 fn deref(&self) -> &Self::Target {
43 &self.0
44 }
45}
46#[doc = "Field `ahb_bridge_fifo_overflow` reader - 1: A ahb FIFO bridge overflow occurred, 0: no overflow occurred"]
47pub struct AHB_BRIDGE_FIFO_OVERFLOW_R(crate::FieldReader<bool, bool>);
48impl AHB_BRIDGE_FIFO_OVERFLOW_R {
49 #[inline(always)]
50 pub(crate) fn new(bits: bool) -> Self {
51 AHB_BRIDGE_FIFO_OVERFLOW_R(crate::FieldReader::new(bits))
52 }
53}
54impl core::ops::Deref for AHB_BRIDGE_FIFO_OVERFLOW_R {
55 type Target = crate::FieldReader<bool, bool>;
56 #[inline(always)]
57 fn deref(&self) -> &Self::Target {
58 &self.0
59 }
60}
61#[doc = "Field `spim_ssi_txe_intr` reader - SPIM Transmit FIFO empty"]
62pub struct SPIM_SSI_TXE_INTR_R(crate::FieldReader<bool, bool>);
63impl SPIM_SSI_TXE_INTR_R {
64 #[inline(always)]
65 pub(crate) fn new(bits: bool) -> Self {
66 SPIM_SSI_TXE_INTR_R(crate::FieldReader::new(bits))
67 }
68}
69impl core::ops::Deref for SPIM_SSI_TXE_INTR_R {
70 type Target = crate::FieldReader<bool, bool>;
71 #[inline(always)]
72 fn deref(&self) -> &Self::Target {
73 &self.0
74 }
75}
76#[doc = "Field `spim_ssi_txo_intr` reader - SPIM Transmit FIFO overflow"]
77pub struct SPIM_SSI_TXO_INTR_R(crate::FieldReader<bool, bool>);
78impl SPIM_SSI_TXO_INTR_R {
79 #[inline(always)]
80 pub(crate) fn new(bits: bool) -> Self {
81 SPIM_SSI_TXO_INTR_R(crate::FieldReader::new(bits))
82 }
83}
84impl core::ops::Deref for SPIM_SSI_TXO_INTR_R {
85 type Target = crate::FieldReader<bool, bool>;
86 #[inline(always)]
87 fn deref(&self) -> &Self::Target {
88 &self.0
89 }
90}
91#[doc = "Field `spim_ssi_rxf_intr` reader - SPIM Receive FIFO threshold"]
92pub struct SPIM_SSI_RXF_INTR_R(crate::FieldReader<bool, bool>);
93impl SPIM_SSI_RXF_INTR_R {
94 #[inline(always)]
95 pub(crate) fn new(bits: bool) -> Self {
96 SPIM_SSI_RXF_INTR_R(crate::FieldReader::new(bits))
97 }
98}
99impl core::ops::Deref for SPIM_SSI_RXF_INTR_R {
100 type Target = crate::FieldReader<bool, bool>;
101 #[inline(always)]
102 fn deref(&self) -> &Self::Target {
103 &self.0
104 }
105}
106#[doc = "Field `spim_ssi_rxo_intr` reader - SPIM Receive FIFO overflow"]
107pub struct SPIM_SSI_RXO_INTR_R(crate::FieldReader<bool, bool>);
108impl SPIM_SSI_RXO_INTR_R {
109 #[inline(always)]
110 pub(crate) fn new(bits: bool) -> Self {
111 SPIM_SSI_RXO_INTR_R(crate::FieldReader::new(bits))
112 }
113}
114impl core::ops::Deref for SPIM_SSI_RXO_INTR_R {
115 type Target = crate::FieldReader<bool, bool>;
116 #[inline(always)]
117 fn deref(&self) -> &Self::Target {
118 &self.0
119 }
120}
121#[doc = "Field `spim_ssi_rxu_intr` reader - SPIM Receive FIFO underflow"]
122pub struct SPIM_SSI_RXU_INTR_R(crate::FieldReader<bool, bool>);
123impl SPIM_SSI_RXU_INTR_R {
124 #[inline(always)]
125 pub(crate) fn new(bits: bool) -> Self {
126 SPIM_SSI_RXU_INTR_R(crate::FieldReader::new(bits))
127 }
128}
129impl core::ops::Deref for SPIM_SSI_RXU_INTR_R {
130 type Target = crate::FieldReader<bool, bool>;
131 #[inline(always)]
132 fn deref(&self) -> &Self::Target {
133 &self.0
134 }
135}
136#[doc = "Field `spim_ssi_mst_intr` reader - SPIM master interrupt"]
137pub struct SPIM_SSI_MST_INTR_R(crate::FieldReader<bool, bool>);
138impl SPIM_SSI_MST_INTR_R {
139 #[inline(always)]
140 pub(crate) fn new(bits: bool) -> Self {
141 SPIM_SSI_MST_INTR_R(crate::FieldReader::new(bits))
142 }
143}
144impl core::ops::Deref for SPIM_SSI_MST_INTR_R {
145 type Target = crate::FieldReader<bool, bool>;
146 #[inline(always)]
147 fn deref(&self) -> &Self::Target {
148 &self.0
149 }
150}
151impl R {
152 #[doc = "Bit 0 - 1: hresp=1, 0: hresp didn't go to 1, write one to clr"]
153 #[inline(always)]
154 pub fn dma_herror(&self) -> DMA_HERROR_R {
155 DMA_HERROR_R::new((self.bits & 0x01) != 0)
156 }
157 #[doc = "Bit 1 - 1: rx threshold was hit, 0:threshold was not hit. This is before external mask bit."]
158 #[inline(always)]
159 pub fn rx_data_available(&self) -> RX_DATA_AVAILABLE_R {
160 RX_DATA_AVAILABLE_R::new(((self.bits >> 1) & 0x01) != 0)
161 }
162 #[doc = "Bit 2 - 1: A ahb FIFO bridge overflow occurred, 0: no overflow occurred"]
163 #[inline(always)]
164 pub fn ahb_bridge_fifo_overflow(&self) -> AHB_BRIDGE_FIFO_OVERFLOW_R {
165 AHB_BRIDGE_FIFO_OVERFLOW_R::new(((self.bits >> 2) & 0x01) != 0)
166 }
167 #[doc = "Bit 3 - SPIM Transmit FIFO empty"]
168 #[inline(always)]
169 pub fn spim_ssi_txe_intr(&self) -> SPIM_SSI_TXE_INTR_R {
170 SPIM_SSI_TXE_INTR_R::new(((self.bits >> 3) & 0x01) != 0)
171 }
172 #[doc = "Bit 4 - SPIM Transmit FIFO overflow"]
173 #[inline(always)]
174 pub fn spim_ssi_txo_intr(&self) -> SPIM_SSI_TXO_INTR_R {
175 SPIM_SSI_TXO_INTR_R::new(((self.bits >> 4) & 0x01) != 0)
176 }
177 #[doc = "Bit 5 - SPIM Receive FIFO threshold"]
178 #[inline(always)]
179 pub fn spim_ssi_rxf_intr(&self) -> SPIM_SSI_RXF_INTR_R {
180 SPIM_SSI_RXF_INTR_R::new(((self.bits >> 5) & 0x01) != 0)
181 }
182 #[doc = "Bit 6 - SPIM Receive FIFO overflow"]
183 #[inline(always)]
184 pub fn spim_ssi_rxo_intr(&self) -> SPIM_SSI_RXO_INTR_R {
185 SPIM_SSI_RXO_INTR_R::new(((self.bits >> 6) & 0x01) != 0)
186 }
187 #[doc = "Bit 7 - SPIM Receive FIFO underflow"]
188 #[inline(always)]
189 pub fn spim_ssi_rxu_intr(&self) -> SPIM_SSI_RXU_INTR_R {
190 SPIM_SSI_RXU_INTR_R::new(((self.bits >> 7) & 0x01) != 0)
191 }
192 #[doc = "Bit 8 - SPIM master interrupt"]
193 #[inline(always)]
194 pub fn spim_ssi_mst_intr(&self) -> SPIM_SSI_MST_INTR_R {
195 SPIM_SSI_MST_INTR_R::new(((self.bits >> 8) & 0x01) != 0)
196 }
197}
198#[doc = "DMA interrupts\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_intr](index.html) module"]
199pub struct DMA_INTR_SPEC;
200impl crate::RegisterSpec for DMA_INTR_SPEC {
201 type Ux = u32;
202}
203#[doc = "`read()` method returns [dma_intr::R](R) reader structure"]
204impl crate::Readable for DMA_INTR_SPEC {
205 type Reader = R;
206}
207#[doc = "`reset()` method sets DMA_INTR to value 0"]
208impl crate::Resettable for DMA_INTR_SPEC {
209 #[inline(always)]
210 fn reset_value() -> Self::Ux {
211 0
212 }
213}