eos_s3/dma/
dma_dest_addr.rs

1#[doc = "Register `DMA_DEST_ADDR` reader"]
2pub struct R(crate::R<DMA_DEST_ADDR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DMA_DEST_ADDR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DMA_DEST_ADDR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DMA_DEST_ADDR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DMA_DEST_ADDR` writer"]
17pub struct W(crate::W<DMA_DEST_ADDR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DMA_DEST_ADDR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DMA_DEST_ADDR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DMA_DEST_ADDR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `dma_dest_addr` reader - DMA output data address : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux."]
38pub struct DMA_DEST_ADDR_R(crate::FieldReader<u32, u32>);
39impl DMA_DEST_ADDR_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: u32) -> Self {
42        DMA_DEST_ADDR_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for DMA_DEST_ADDR_R {
46    type Target = crate::FieldReader<u32, u32>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `dma_dest_addr` writer - DMA output data address : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux."]
53pub struct DMA_DEST_ADDR_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> DMA_DEST_ADDR_W<'a> {
57    #[doc = r"Writes raw bits to the field"]
58    #[inline(always)]
59    pub unsafe fn bits(self, value: u32) -> &'a mut W {
60        self.w.bits = value as u32;
61        self.w
62    }
63}
64impl R {
65    #[doc = "Bits 0:31 - DMA output data address : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux."]
66    #[inline(always)]
67    pub fn dma_dest_addr(&self) -> DMA_DEST_ADDR_R {
68        DMA_DEST_ADDR_R::new(self.bits as u32)
69    }
70}
71impl W {
72    #[doc = "Bits 0:31 - DMA output data address : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux."]
73    #[inline(always)]
74    pub fn dma_dest_addr(&mut self) -> DMA_DEST_ADDR_W {
75        DMA_DEST_ADDR_W { w: self }
76    }
77    #[doc = "Writes raw bits to the register."]
78    #[inline(always)]
79    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
80        self.0.bits(bits);
81        self
82    }
83}
84#[doc = "DMA destination address : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_dest_addr](index.html) module"]
85pub struct DMA_DEST_ADDR_SPEC;
86impl crate::RegisterSpec for DMA_DEST_ADDR_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [dma_dest_addr::R](R) reader structure"]
90impl crate::Readable for DMA_DEST_ADDR_SPEC {
91    type Reader = R;
92}
93#[doc = "`write(|w| ..)` method takes [dma_dest_addr::W](W) writer structure"]
94impl crate::Writable for DMA_DEST_ADDR_SPEC {
95    type Writer = W;
96}
97#[doc = "`reset()` method sets DMA_DEST_ADDR to value 0"]
98impl crate::Resettable for DMA_DEST_ADDR_SPEC {
99    #[inline(always)]
100    fn reset_value() -> Self::Ux {
101        0
102    }
103}
eos_s3/dma/dma_dest_addr.rs

eos_s3/dma/
dma_dest_addr.rs
