eos_s3/dma/
cfg_flash_header.rs

1#[doc = "Register `CFG_FLASH_HEADER` reader"]
2pub struct R(crate::R<CFG_FLASH_HEADER_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFG_FLASH_HEADER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFG_FLASH_HEADER_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFG_FLASH_HEADER_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `dma_boot_xfr_size` reader - number of double words (8 bytes) for the SPI to transfer (minus 1)"]
17pub struct DMA_BOOT_XFR_SIZE_R(crate::FieldReader<u16, u16>);
18impl DMA_BOOT_XFR_SIZE_R {
19    #[inline(always)]
20    pub(crate) fn new(bits: u16) -> Self {
21        DMA_BOOT_XFR_SIZE_R(crate::FieldReader::new(bits))
22    }
23}
24impl core::ops::Deref for DMA_BOOT_XFR_SIZE_R {
25    type Target = crate::FieldReader<u16, u16>;
26    #[inline(always)]
27    fn deref(&self) -> &Self::Target {
28        &self.0
29    }
30}
31#[doc = "Field `dma_spi_clik_divide` reader - SPI data clock out divides the ssi_clk (value in bytes*2)"]
32pub struct DMA_SPI_CLIK_DIVIDE_R(crate::FieldReader<u8, u8>);
33impl DMA_SPI_CLIK_DIVIDE_R {
34    #[inline(always)]
35    pub(crate) fn new(bits: u8) -> Self {
36        DMA_SPI_CLIK_DIVIDE_R(crate::FieldReader::new(bits))
37    }
38}
39impl core::ops::Deref for DMA_SPI_CLIK_DIVIDE_R {
40    type Target = crate::FieldReader<u8, u8>;
41    #[inline(always)]
42    fn deref(&self) -> &Self::Target {
43        &self.0
44    }
45}
46#[doc = "Field `dma_device_id` reader - Device ID"]
47pub struct DMA_DEVICE_ID_R(crate::FieldReader<u8, u8>);
48impl DMA_DEVICE_ID_R {
49    #[inline(always)]
50    pub(crate) fn new(bits: u8) -> Self {
51        DMA_DEVICE_ID_R(crate::FieldReader::new(bits))
52    }
53}
54impl core::ops::Deref for DMA_DEVICE_ID_R {
55    type Target = crate::FieldReader<u8, u8>;
56    #[inline(always)]
57    fn deref(&self) -> &Self::Target {
58        &self.0
59    }
60}
61impl R {
62    #[doc = "Bits 0:15 - number of double words (8 bytes) for the SPI to transfer (minus 1)"]
63    #[inline(always)]
64    pub fn dma_boot_xfr_size(&self) -> DMA_BOOT_XFR_SIZE_R {
65        DMA_BOOT_XFR_SIZE_R::new((self.bits & 0xffff) as u16)
66    }
67    #[doc = "Bits 16:23 - SPI data clock out divides the ssi_clk (value in bytes*2)"]
68    #[inline(always)]
69    pub fn dma_spi_clik_divide(&self) -> DMA_SPI_CLIK_DIVIDE_R {
70        DMA_SPI_CLIK_DIVIDE_R::new(((self.bits >> 16) & 0xff) as u8)
71    }
72    #[doc = "Bits 24:31 - Device ID"]
73    #[inline(always)]
74    pub fn dma_device_id(&self) -> DMA_DEVICE_ID_R {
75        DMA_DEVICE_ID_R::new(((self.bits >> 24) & 0xff) as u8)
76    }
77}
78#[doc = "Header values read from EEPROM : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg_flash_header](index.html) module"]
79pub struct CFG_FLASH_HEADER_SPEC;
80impl crate::RegisterSpec for CFG_FLASH_HEADER_SPEC {
81    type Ux = u32;
82}
83#[doc = "`read()` method returns [cfg_flash_header::R](R) reader structure"]
84impl crate::Readable for CFG_FLASH_HEADER_SPEC {
85    type Reader = R;
86}
87#[doc = "`reset()` method sets CFG_FLASH_HEADER to value 0"]
88impl crate::Resettable for CFG_FLASH_HEADER_SPEC {
89    #[inline(always)]
90    fn reset_value() -> Self::Ux {
91        0
92    }
93}
eos_s3/dma/cfg_flash_header.rs

eos_s3/dma/
cfg_flash_header.rs
