eos_s3/
dma.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    _reserved_0_dma_ctrl: [u8; 0x04],
5    #[doc = "0x04 - DMA destination address : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux."]
6    pub dma_dest_addr: crate::Reg<dma_dest_addr::DMA_DEST_ADDR_SPEC>,
7    #[doc = "0x08 - DMA transfer count in frames (8 bit) (minus 1) : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux."]
8    pub dma_xfer_cnt: crate::Reg<dma_xfer_cnt::DMA_XFER_CNT_SPEC>,
9    #[doc = "0x0c - Header values read from EEPROM : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux."]
10    pub cfg_flash_header: crate::Reg<cfg_flash_header::CFG_FLASH_HEADER_SPEC>,
11    #[doc = "0x10 - DMA interrupts"]
12    pub dma_intr: crate::Reg<dma_intr::DMA_INTR_SPEC>,
13    #[doc = "0x14 - DMA interrupt mask"]
14    pub dma_intr_mask: crate::Reg<dma_intr_mask::DMA_INTR_MASK_SPEC>,
15}
16impl RegisterBlock {
17    #[doc = "0x00 - This is the delay value used in the config state machine. It is used for both deep sleep wakeup delay and between retries."]
18    #[inline(always)]
19    pub fn cfg_machine_st_delay(
20        &self,
21    ) -> &crate::Reg<cfg_machine_st_delay::CFG_MACHINE_ST_DELAY_SPEC> {
22        unsafe {
23            &*(((self as *const Self) as *const u8).add(0usize)
24                as *const crate::Reg<
25                    cfg_machine_st_delay::CFG_MACHINE_ST_DELAY_SPEC,
26                >)
27        }
28    }
29    #[doc = "0x00 - DMA Control : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux."]
30    #[inline(always)]
31    pub fn dma_ctrl(&self) -> &crate::Reg<dma_ctrl::DMA_CTRL_SPEC> {
32        unsafe {
33            &*(((self as *const Self) as *const u8).add(0usize)
34                as *const crate::Reg<dma_ctrl::DMA_CTRL_SPEC>)
35        }
36    }
37}
38#[doc = "DMA_CTRL register accessor: an alias for `Reg<DMA_CTRL_SPEC>`"]
39pub type DMA_CTRL = crate::Reg<dma_ctrl::DMA_CTRL_SPEC>;
40#[doc = "DMA Control : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux."]
41pub mod dma_ctrl;
42#[doc = "DMA_DEST_ADDR register accessor: an alias for `Reg<DMA_DEST_ADDR_SPEC>`"]
43pub type DMA_DEST_ADDR = crate::Reg<dma_dest_addr::DMA_DEST_ADDR_SPEC>;
44#[doc = "DMA destination address : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux."]
45pub mod dma_dest_addr;
46#[doc = "DMA_XFER_CNT register accessor: an alias for `Reg<DMA_XFER_CNT_SPEC>`"]
47pub type DMA_XFER_CNT = crate::Reg<dma_xfer_cnt::DMA_XFER_CNT_SPEC>;
48#[doc = "DMA transfer count in frames (8 bit) (minus 1) : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux."]
49pub mod dma_xfer_cnt;
50#[doc = "CFG_FLASH_HEADER register accessor: an alias for `Reg<CFG_FLASH_HEADER_SPEC>`"]
51pub type CFG_FLASH_HEADER = crate::Reg<cfg_flash_header::CFG_FLASH_HEADER_SPEC>;
52#[doc = "Header values read from EEPROM : this register is only accessable when the dma or cfg_sm is not selecting the dmas_mux."]
53pub mod cfg_flash_header;
54#[doc = "DMA_INTR register accessor: an alias for `Reg<DMA_INTR_SPEC>`"]
55pub type DMA_INTR = crate::Reg<dma_intr::DMA_INTR_SPEC>;
56#[doc = "DMA interrupts"]
57pub mod dma_intr;
58#[doc = "DMA_INTR_MASK register accessor: an alias for `Reg<DMA_INTR_MASK_SPEC>`"]
59pub type DMA_INTR_MASK = crate::Reg<dma_intr_mask::DMA_INTR_MASK_SPEC>;
60#[doc = "DMA interrupt mask"]
61pub mod dma_intr_mask;
62#[doc = "CFG_MACHINE_ST_DELAY register accessor: an alias for `Reg<CFG_MACHINE_ST_DELAY_SPEC>`"]
63pub type CFG_MACHINE_ST_DELAY =
64    crate::Reg<cfg_machine_st_delay::CFG_MACHINE_ST_DELAY_SPEC>;
65#[doc = "This is the delay value used in the config state machine. It is used for both deep sleep wakeup delay and between retries."]
66pub mod cfg_machine_st_delay;
eos_s3/dma.rs

eos_s3/
dma.rs
