eos_s3/cru/
clk_switch_for_h.rs

1#[doc = "Register `CLK_SWITCH_FOR_H` reader"]
2pub struct R(crate::R<CLK_SWITCH_FOR_H_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLK_SWITCH_FOR_H_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLK_SWITCH_FOR_H_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLK_SWITCH_FOR_H_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CLK_SWITCH_FOR_H` writer"]
17pub struct W(crate::W<CLK_SWITCH_FOR_H_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLK_SWITCH_FOR_H_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLK_SWITCH_FOR_H_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLK_SWITCH_FOR_H_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Choose between High Speed Clock or 32Khz oscillator\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum CLOCK_SOURCE_SELECTION_A {
40    #[doc = "0: Selects the High speed/Divided clock"]
41    WITH_HS_CLK = 0,
42    #[doc = "1: Selects the 32KHz oscillator"]
43    WITH_32KHZ_CLK = 1,
44}
45impl From<CLOCK_SOURCE_SELECTION_A> for bool {
46    #[inline(always)]
47    fn from(variant: CLOCK_SOURCE_SELECTION_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `Clock_Source_Selection` reader - Choose between High Speed Clock or 32Khz oscillator"]
52pub struct CLOCK_SOURCE_SELECTION_R(
53    crate::FieldReader<bool, CLOCK_SOURCE_SELECTION_A>,
54);
55impl CLOCK_SOURCE_SELECTION_R {
56    #[inline(always)]
57    pub(crate) fn new(bits: bool) -> Self {
58        CLOCK_SOURCE_SELECTION_R(crate::FieldReader::new(bits))
59    }
60    #[doc = r"Get enumerated values variant"]
61    #[inline(always)]
62    pub fn variant(&self) -> CLOCK_SOURCE_SELECTION_A {
63        match self.bits {
64            false => CLOCK_SOURCE_SELECTION_A::WITH_HS_CLK,
65            true => CLOCK_SOURCE_SELECTION_A::WITH_32KHZ_CLK,
66        }
67    }
68    #[doc = "Checks if the value of the field is `WITH_HS_CLK`"]
69    #[inline(always)]
70    pub fn is_with_hs_clk(&self) -> bool {
71        **self == CLOCK_SOURCE_SELECTION_A::WITH_HS_CLK
72    }
73    #[doc = "Checks if the value of the field is `WITH_32KHZ_CLK`"]
74    #[inline(always)]
75    pub fn is_with_32khz_clk(&self) -> bool {
76        **self == CLOCK_SOURCE_SELECTION_A::WITH_32KHZ_CLK
77    }
78}
79impl core::ops::Deref for CLOCK_SOURCE_SELECTION_R {
80    type Target = crate::FieldReader<bool, CLOCK_SOURCE_SELECTION_A>;
81    #[inline(always)]
82    fn deref(&self) -> &Self::Target {
83        &self.0
84    }
85}
86#[doc = "Field `Clock_Source_Selection` writer - Choose between High Speed Clock or 32Khz oscillator"]
87pub struct CLOCK_SOURCE_SELECTION_W<'a> {
88    w: &'a mut W,
89}
90impl<'a> CLOCK_SOURCE_SELECTION_W<'a> {
91    #[doc = r"Writes `variant` to the field"]
92    #[inline(always)]
93    pub fn variant(self, variant: CLOCK_SOURCE_SELECTION_A) -> &'a mut W {
94        self.bit(variant.into())
95    }
96    #[doc = "Selects the High speed/Divided clock"]
97    #[inline(always)]
98    pub fn with_hs_clk(self) -> &'a mut W {
99        self.variant(CLOCK_SOURCE_SELECTION_A::WITH_HS_CLK)
100    }
101    #[doc = "Selects the 32KHz oscillator"]
102    #[inline(always)]
103    pub fn with_32khz_clk(self) -> &'a mut W {
104        self.variant(CLOCK_SOURCE_SELECTION_A::WITH_32KHZ_CLK)
105    }
106    #[doc = r"Sets the field bit"]
107    #[inline(always)]
108    pub fn set_bit(self) -> &'a mut W {
109        self.bit(true)
110    }
111    #[doc = r"Clears the field bit"]
112    #[inline(always)]
113    pub fn clear_bit(self) -> &'a mut W {
114        self.bit(false)
115    }
116    #[doc = r"Writes raw bits to the field"]
117    #[inline(always)]
118    pub fn bit(self, value: bool) -> &'a mut W {
119        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
120        self.w
121    }
122}
123impl R {
124    #[doc = "Bit 0 - Choose between High Speed Clock or 32Khz oscillator"]
125    #[inline(always)]
126    pub fn clock_source_selection(&self) -> CLOCK_SOURCE_SELECTION_R {
127        CLOCK_SOURCE_SELECTION_R::new((self.bits & 0x01) != 0)
128    }
129}
130impl W {
131    #[doc = "Bit 0 - Choose between High Speed Clock or 32Khz oscillator"]
132    #[inline(always)]
133    pub fn clock_source_selection(&mut self) -> CLOCK_SOURCE_SELECTION_W {
134        CLOCK_SOURCE_SELECTION_W { w: self }
135    }
136    #[doc = "Writes raw bits to the register."]
137    #[inline(always)]
138    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
139        self.0.bits(bits);
140        self
141    }
142}
143#[doc = "For Clock 19 (ADC)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_switch_for_h](index.html) module"]
144pub struct CLK_SWITCH_FOR_H_SPEC;
145impl crate::RegisterSpec for CLK_SWITCH_FOR_H_SPEC {
146    type Ux = u32;
147}
148#[doc = "`read()` method returns [clk_switch_for_h::R](R) reader structure"]
149impl crate::Readable for CLK_SWITCH_FOR_H_SPEC {
150    type Reader = R;
151}
152#[doc = "`write(|w| ..)` method takes [clk_switch_for_h::W](W) writer structure"]
153impl crate::Writable for CLK_SWITCH_FOR_H_SPEC {
154    type Writer = W;
155}
156#[doc = "`reset()` method sets CLK_SWITCH_FOR_H to value 0"]
157impl crate::Resettable for CLK_SWITCH_FOR_H_SPEC {
158    #[inline(always)]
159    fn reset_value() -> Self::Ux {
160        0
161    }
162}
eos_s3/cru/clk_switch_for_h.rs

eos_s3/cru/
clk_switch_for_h.rs
