eos_s3/cru/
clk_ctrl_pmu.rs

1#[doc = "Register `CLK_CTRL_PMU` reader"]
2pub struct R(crate::R<CLK_CTRL_PMU_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLK_CTRL_PMU_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLK_CTRL_PMU_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLK_CTRL_PMU_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CLK_CTRL_PMU` writer"]
17pub struct W(crate::W<CLK_CTRL_PMU_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLK_CTRL_PMU_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLK_CTRL_PMU_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLK_CTRL_PMU_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `Clock_Divider_Ratio` reader - High Speed Clock Divider Ratio. Ratio is reg value + 2. default div is 64"]
38pub struct CLOCK_DIVIDER_RATIO_R(crate::FieldReader<u16, u16>);
39impl CLOCK_DIVIDER_RATIO_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: u16) -> Self {
42        CLOCK_DIVIDER_RATIO_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for CLOCK_DIVIDER_RATIO_R {
46    type Target = crate::FieldReader<u16, u16>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `Clock_Divider_Ratio` writer - High Speed Clock Divider Ratio. Ratio is reg value + 2. default div is 64"]
53pub struct CLOCK_DIVIDER_RATIO_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> CLOCK_DIVIDER_RATIO_W<'a> {
57    #[doc = r"Writes raw bits to the field"]
58    #[inline(always)]
59    pub unsafe fn bits(self, value: u16) -> &'a mut W {
60        self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff);
61        self.w
62    }
63}
64#[doc = "1'b1 Clock Divider is ON. 1'b0 Clock Divider is OFF, Output the Source Clock Directly\n\nValue on reset: 1"]
65#[derive(Clone, Copy, Debug, PartialEq)]
66pub enum ENABLE_CLOCK_DIVIDER_A {
67    #[doc = "0: Clock divider is OFF, Output Source clock directly"]
68    DISABLE = 0,
69    #[doc = "1: Clock divider is ON"]
70    ENABLE = 1,
71}
72impl From<ENABLE_CLOCK_DIVIDER_A> for bool {
73    #[inline(always)]
74    fn from(variant: ENABLE_CLOCK_DIVIDER_A) -> Self {
75        variant as u8 != 0
76    }
77}
78#[doc = "Field `Enable_Clock_Divider` reader - 1'b1 Clock Divider is ON. 1'b0 Clock Divider is OFF, Output the Source Clock Directly"]
79pub struct ENABLE_CLOCK_DIVIDER_R(
80    crate::FieldReader<bool, ENABLE_CLOCK_DIVIDER_A>,
81);
82impl ENABLE_CLOCK_DIVIDER_R {
83    #[inline(always)]
84    pub(crate) fn new(bits: bool) -> Self {
85        ENABLE_CLOCK_DIVIDER_R(crate::FieldReader::new(bits))
86    }
87    #[doc = r"Get enumerated values variant"]
88    #[inline(always)]
89    pub fn variant(&self) -> ENABLE_CLOCK_DIVIDER_A {
90        match self.bits {
91            false => ENABLE_CLOCK_DIVIDER_A::DISABLE,
92            true => ENABLE_CLOCK_DIVIDER_A::ENABLE,
93        }
94    }
95    #[doc = "Checks if the value of the field is `DISABLE`"]
96    #[inline(always)]
97    pub fn is_disable(&self) -> bool {
98        **self == ENABLE_CLOCK_DIVIDER_A::DISABLE
99    }
100    #[doc = "Checks if the value of the field is `ENABLE`"]
101    #[inline(always)]
102    pub fn is_enable(&self) -> bool {
103        **self == ENABLE_CLOCK_DIVIDER_A::ENABLE
104    }
105}
106impl core::ops::Deref for ENABLE_CLOCK_DIVIDER_R {
107    type Target = crate::FieldReader<bool, ENABLE_CLOCK_DIVIDER_A>;
108    #[inline(always)]
109    fn deref(&self) -> &Self::Target {
110        &self.0
111    }
112}
113#[doc = "Field `Enable_Clock_Divider` writer - 1'b1 Clock Divider is ON. 1'b0 Clock Divider is OFF, Output the Source Clock Directly"]
114pub struct ENABLE_CLOCK_DIVIDER_W<'a> {
115    w: &'a mut W,
116}
117impl<'a> ENABLE_CLOCK_DIVIDER_W<'a> {
118    #[doc = r"Writes `variant` to the field"]
119    #[inline(always)]
120    pub fn variant(self, variant: ENABLE_CLOCK_DIVIDER_A) -> &'a mut W {
121        self.bit(variant.into())
122    }
123    #[doc = "Clock divider is OFF, Output Source clock directly"]
124    #[inline(always)]
125    pub fn disable(self) -> &'a mut W {
126        self.variant(ENABLE_CLOCK_DIVIDER_A::DISABLE)
127    }
128    #[doc = "Clock divider is ON"]
129    #[inline(always)]
130    pub fn enable(self) -> &'a mut W {
131        self.variant(ENABLE_CLOCK_DIVIDER_A::ENABLE)
132    }
133    #[doc = r"Sets the field bit"]
134    #[inline(always)]
135    pub fn set_bit(self) -> &'a mut W {
136        self.bit(true)
137    }
138    #[doc = r"Clears the field bit"]
139    #[inline(always)]
140    pub fn clear_bit(self) -> &'a mut W {
141        self.bit(false)
142    }
143    #[doc = r"Writes raw bits to the field"]
144    #[inline(always)]
145    pub fn bit(self, value: bool) -> &'a mut W {
146        self.w.bits =
147            (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
148        self.w
149    }
150}
151impl R {
152    #[doc = "Bits 0:8 - High Speed Clock Divider Ratio. Ratio is reg value + 2. default div is 64"]
153    #[inline(always)]
154    pub fn clock_divider_ratio(&self) -> CLOCK_DIVIDER_RATIO_R {
155        CLOCK_DIVIDER_RATIO_R::new((self.bits & 0x01ff) as u16)
156    }
157    #[doc = "Bit 9 - 1'b1 Clock Divider is ON. 1'b0 Clock Divider is OFF, Output the Source Clock Directly"]
158    #[inline(always)]
159    pub fn enable_clock_divider(&self) -> ENABLE_CLOCK_DIVIDER_R {
160        ENABLE_CLOCK_DIVIDER_R::new(((self.bits >> 9) & 0x01) != 0)
161    }
162}
163impl W {
164    #[doc = "Bits 0:8 - High Speed Clock Divider Ratio. Ratio is reg value + 2. default div is 64"]
165    #[inline(always)]
166    pub fn clock_divider_ratio(&mut self) -> CLOCK_DIVIDER_RATIO_W {
167        CLOCK_DIVIDER_RATIO_W { w: self }
168    }
169    #[doc = "Bit 9 - 1'b1 Clock Divider is ON. 1'b0 Clock Divider is OFF, Output the Source Clock Directly"]
170    #[inline(always)]
171    pub fn enable_clock_divider(&mut self) -> ENABLE_CLOCK_DIVIDER_W {
172        ENABLE_CLOCK_DIVIDER_W { w: self }
173    }
174    #[doc = "Writes raw bits to the register."]
175    #[inline(always)]
176    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
177        self.0.bits(bits);
178        self
179    }
180}
181#[doc = "This Clock is used to delay the Clock gating control signals from PMU. The PMU will monitor the feedback/delayed Clock Gating Control signals to ensure the clocks are OFF before jump to next state. The Firmware needs to Configure this divider to ensure there delay time is longer enough. C23 Clock needs to be 2/3 of the lowest clock frequency of other clocks. For Example, if the Lowest clock frequency of other clocks are 5, then C23 should be lower than 3.33MHz (Or the clock frequency of other clocks should be at least 1.5 times faster than C23.)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_ctrl_pmu](index.html) module"]
182pub struct CLK_CTRL_PMU_SPEC;
183impl crate::RegisterSpec for CLK_CTRL_PMU_SPEC {
184    type Ux = u32;
185}
186#[doc = "`read()` method returns [clk_ctrl_pmu::R](R) reader structure"]
187impl crate::Readable for CLK_CTRL_PMU_SPEC {
188    type Reader = R;
189}
190#[doc = "`write(|w| ..)` method takes [clk_ctrl_pmu::W](W) writer structure"]
191impl crate::Writable for CLK_CTRL_PMU_SPEC {
192    type Writer = W;
193}
194#[doc = "`reset()` method sets CLK_CTRL_PMU to value 0x023e"]
195impl crate::Resettable for CLK_CTRL_PMU_SPEC {
196    #[inline(always)]
197    fn reset_value() -> Self::Ux {
198        0x023e
199    }
200}
eos_s3/cru/clk_ctrl_pmu.rs

eos_s3/cru/
clk_ctrl_pmu.rs
