eos_s3/cru/
clk_ctrl_e_1.rs

1#[doc = "Register `CLK_CTRL_E_1` reader"]
2pub struct R(crate::R<CLK_CTRL_E_1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLK_CTRL_E_1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLK_CTRL_E_1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLK_CTRL_E_1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "The selected the clock source\n\nValue on reset: 0"]
17#[derive(Clone, Copy, Debug, PartialEq)]
18#[repr(u8)]
19pub enum CLOCK_SOURCE_SELECTION_A {
20    #[doc = "0: Selects the High speed/Divided clock"]
21    WITH_HS_CLK = 0,
22}
23impl From<CLOCK_SOURCE_SELECTION_A> for u8 {
24    #[inline(always)]
25    fn from(variant: CLOCK_SOURCE_SELECTION_A) -> Self {
26        variant as _
27    }
28}
29#[doc = "Field `Clock_Source_Selection` reader - The selected the clock source"]
30pub struct CLOCK_SOURCE_SELECTION_R(
31    crate::FieldReader<u8, CLOCK_SOURCE_SELECTION_A>,
32);
33impl CLOCK_SOURCE_SELECTION_R {
34    #[inline(always)]
35    pub(crate) fn new(bits: u8) -> Self {
36        CLOCK_SOURCE_SELECTION_R(crate::FieldReader::new(bits))
37    }
38    #[doc = r"Get enumerated values variant"]
39    #[inline(always)]
40    pub fn variant(&self) -> Option<CLOCK_SOURCE_SELECTION_A> {
41        match self.bits {
42            0 => Some(CLOCK_SOURCE_SELECTION_A::WITH_HS_CLK),
43            _ => None,
44        }
45    }
46    #[doc = "Checks if the value of the field is `WITH_HS_CLK`"]
47    #[inline(always)]
48    pub fn is_with_hs_clk(&self) -> bool {
49        **self == CLOCK_SOURCE_SELECTION_A::WITH_HS_CLK
50    }
51}
52impl core::ops::Deref for CLOCK_SOURCE_SELECTION_R {
53    type Target = crate::FieldReader<u8, CLOCK_SOURCE_SELECTION_A>;
54    #[inline(always)]
55    fn deref(&self) -> &Self::Target {
56        &self.0
57    }
58}
59impl R {
60    #[doc = "Bits 0:1 - The selected the clock source"]
61    #[inline(always)]
62    pub fn clock_source_selection(&self) -> CLOCK_SOURCE_SELECTION_R {
63        CLOCK_SOURCE_SELECTION_R::new((self.bits & 0x03) as u8)
64    }
65}
66#[doc = "For Clock 12\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_ctrl_e_1](index.html) module"]
67pub struct CLK_CTRL_E_1_SPEC;
68impl crate::RegisterSpec for CLK_CTRL_E_1_SPEC {
69    type Ux = u32;
70}
71#[doc = "`read()` method returns [clk_ctrl_e_1::R](R) reader structure"]
72impl crate::Readable for CLK_CTRL_E_1_SPEC {
73    type Reader = R;
74}
75#[doc = "`reset()` method sets CLK_CTRL_E_1 to value 0"]
76impl crate::Resettable for CLK_CTRL_E_1_SPEC {
77    #[inline(always)]
78    fn reset_value() -> Self::Ux {
79        0
80    }
81}
eos_s3/cru/clk_ctrl_e_1.rs

eos_s3/cru/
clk_ctrl_e_1.rs
