eos_s3/cru/
c10_fclk_gate.rs

1#[doc = "Register `C10_FCLK_GATE` reader"]
2pub struct R(crate::R<C10_FCLK_GATE_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<C10_FCLK_GATE_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<C10_FCLK_GATE_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<C10_FCLK_GATE_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `C10_FCLK_GATE` writer"]
17pub struct W(crate::W<C10_FCLK_GATE_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<C10_FCLK_GATE_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<C10_FCLK_GATE_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<C10_FCLK_GATE_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "To M4 Bus Matrix and Trace block\n\nValue on reset: 1"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum PATH_0_GATING_CONTROL_A {
40    #[doc = "0: Clock is stop"]
41    STOP = 0,
42    #[doc = "1: Clock is runnig"]
43    RUN = 1,
44}
45impl From<PATH_0_GATING_CONTROL_A> for bool {
46    #[inline(always)]
47    fn from(variant: PATH_0_GATING_CONTROL_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `Path_0_Gating_Control` reader - To M4 Bus Matrix and Trace block"]
52pub struct PATH_0_GATING_CONTROL_R(
53    crate::FieldReader<bool, PATH_0_GATING_CONTROL_A>,
54);
55impl PATH_0_GATING_CONTROL_R {
56    #[inline(always)]
57    pub(crate) fn new(bits: bool) -> Self {
58        PATH_0_GATING_CONTROL_R(crate::FieldReader::new(bits))
59    }
60    #[doc = r"Get enumerated values variant"]
61    #[inline(always)]
62    pub fn variant(&self) -> PATH_0_GATING_CONTROL_A {
63        match self.bits {
64            false => PATH_0_GATING_CONTROL_A::STOP,
65            true => PATH_0_GATING_CONTROL_A::RUN,
66        }
67    }
68    #[doc = "Checks if the value of the field is `STOP`"]
69    #[inline(always)]
70    pub fn is_stop(&self) -> bool {
71        **self == PATH_0_GATING_CONTROL_A::STOP
72    }
73    #[doc = "Checks if the value of the field is `RUN`"]
74    #[inline(always)]
75    pub fn is_run(&self) -> bool {
76        **self == PATH_0_GATING_CONTROL_A::RUN
77    }
78}
79impl core::ops::Deref for PATH_0_GATING_CONTROL_R {
80    type Target = crate::FieldReader<bool, PATH_0_GATING_CONTROL_A>;
81    #[inline(always)]
82    fn deref(&self) -> &Self::Target {
83        &self.0
84    }
85}
86#[doc = "RWHC: To M4 SRAM Instance, M4S0~M4S3. This bit will be set if any of the Memories (M4S0~M4S3) been wakeup by Hardware."]
87pub type PATH_1_GATING_CONTROL_A = PATH_0_GATING_CONTROL_A;
88#[doc = "Field `Path_1_Gating_Control` reader - RWHC: To M4 SRAM Instance, M4S0~M4S3. This bit will be set if any of the Memories (M4S0~M4S3) been wakeup by Hardware."]
89pub type PATH_1_GATING_CONTROL_R = PATH_0_GATING_CONTROL_R;
90#[doc = "Field `Path_1_Gating_Control` writer - RWHC: To M4 SRAM Instance, M4S0~M4S3. This bit will be set if any of the Memories (M4S0~M4S3) been wakeup by Hardware."]
91pub struct PATH_1_GATING_CONTROL_W<'a> {
92    w: &'a mut W,
93}
94impl<'a> PATH_1_GATING_CONTROL_W<'a> {
95    #[doc = r"Writes `variant` to the field"]
96    #[inline(always)]
97    pub fn variant(self, variant: PATH_1_GATING_CONTROL_A) -> &'a mut W {
98        self.bit(variant.into())
99    }
100    #[doc = "Clock is stop"]
101    #[inline(always)]
102    pub fn stop(self) -> &'a mut W {
103        self.variant(PATH_1_GATING_CONTROL_A::STOP)
104    }
105    #[doc = "Clock is runnig"]
106    #[inline(always)]
107    pub fn run(self) -> &'a mut W {
108        self.variant(PATH_1_GATING_CONTROL_A::RUN)
109    }
110    #[doc = r"Sets the field bit"]
111    #[inline(always)]
112    pub fn set_bit(self) -> &'a mut W {
113        self.bit(true)
114    }
115    #[doc = r"Clears the field bit"]
116    #[inline(always)]
117    pub fn clear_bit(self) -> &'a mut W {
118        self.bit(false)
119    }
120    #[doc = r"Writes raw bits to the field"]
121    #[inline(always)]
122    pub fn bit(self, value: bool) -> &'a mut W {
123        self.w.bits =
124            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
125        self.w
126    }
127}
128#[doc = "RWHC: To M4 SRAM Instance, M4S4~M4S7. This bit will be set if any of the Memories (M4S4~M4S7) been wakeup by Hardware."]
129pub type PATH_2_GATING_CONTROL_A = PATH_0_GATING_CONTROL_A;
130#[doc = "Field `Path_2_Gating_Control` reader - RWHC: To M4 SRAM Instance, M4S4~M4S7. This bit will be set if any of the Memories (M4S4~M4S7) been wakeup by Hardware."]
131pub type PATH_2_GATING_CONTROL_R = PATH_0_GATING_CONTROL_R;
132#[doc = "Field `Path_2_Gating_Control` writer - RWHC: To M4 SRAM Instance, M4S4~M4S7. This bit will be set if any of the Memories (M4S4~M4S7) been wakeup by Hardware."]
133pub struct PATH_2_GATING_CONTROL_W<'a> {
134    w: &'a mut W,
135}
136impl<'a> PATH_2_GATING_CONTROL_W<'a> {
137    #[doc = r"Writes `variant` to the field"]
138    #[inline(always)]
139    pub fn variant(self, variant: PATH_2_GATING_CONTROL_A) -> &'a mut W {
140        self.bit(variant.into())
141    }
142    #[doc = "Clock is stop"]
143    #[inline(always)]
144    pub fn stop(self) -> &'a mut W {
145        self.variant(PATH_2_GATING_CONTROL_A::STOP)
146    }
147    #[doc = "Clock is runnig"]
148    #[inline(always)]
149    pub fn run(self) -> &'a mut W {
150        self.variant(PATH_2_GATING_CONTROL_A::RUN)
151    }
152    #[doc = r"Sets the field bit"]
153    #[inline(always)]
154    pub fn set_bit(self) -> &'a mut W {
155        self.bit(true)
156    }
157    #[doc = r"Clears the field bit"]
158    #[inline(always)]
159    pub fn clear_bit(self) -> &'a mut W {
160        self.bit(false)
161    }
162    #[doc = r"Writes raw bits to the field"]
163    #[inline(always)]
164    pub fn bit(self, value: bool) -> &'a mut W {
165        self.w.bits =
166            (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
167        self.w
168    }
169}
170#[doc = "RWHC: To M4 SRAM Instance, M4S8~M4S11. This bit will be set if any of the Memories (M4S8~M4S11) been wakeup by Hardware."]
171pub type PATH_3_GATING_CONTROL_A = PATH_0_GATING_CONTROL_A;
172#[doc = "Field `Path_3_Gating_Control` reader - RWHC: To M4 SRAM Instance, M4S8~M4S11. This bit will be set if any of the Memories (M4S8~M4S11) been wakeup by Hardware."]
173pub type PATH_3_GATING_CONTROL_R = PATH_0_GATING_CONTROL_R;
174#[doc = "Field `Path_3_Gating_Control` writer - RWHC: To M4 SRAM Instance, M4S8~M4S11. This bit will be set if any of the Memories (M4S8~M4S11) been wakeup by Hardware."]
175pub struct PATH_3_GATING_CONTROL_W<'a> {
176    w: &'a mut W,
177}
178impl<'a> PATH_3_GATING_CONTROL_W<'a> {
179    #[doc = r"Writes `variant` to the field"]
180    #[inline(always)]
181    pub fn variant(self, variant: PATH_3_GATING_CONTROL_A) -> &'a mut W {
182        self.bit(variant.into())
183    }
184    #[doc = "Clock is stop"]
185    #[inline(always)]
186    pub fn stop(self) -> &'a mut W {
187        self.variant(PATH_3_GATING_CONTROL_A::STOP)
188    }
189    #[doc = "Clock is runnig"]
190    #[inline(always)]
191    pub fn run(self) -> &'a mut W {
192        self.variant(PATH_3_GATING_CONTROL_A::RUN)
193    }
194    #[doc = r"Sets the field bit"]
195    #[inline(always)]
196    pub fn set_bit(self) -> &'a mut W {
197        self.bit(true)
198    }
199    #[doc = r"Clears the field bit"]
200    #[inline(always)]
201    pub fn clear_bit(self) -> &'a mut W {
202        self.bit(false)
203    }
204    #[doc = r"Writes raw bits to the field"]
205    #[inline(always)]
206    pub fn bit(self, value: bool) -> &'a mut W {
207        self.w.bits =
208            (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
209        self.w
210    }
211}
212#[doc = "RWHC: To M4 SRAM Instance, M4S12~M4S15. This bit will be set if any of the Memories (M4S12~M4S15) been wakeup by Hardware."]
213pub type PATH_4_GATING_CONTROL_A = PATH_0_GATING_CONTROL_A;
214#[doc = "Field `Path_4_Gating_Control` reader - RWHC: To M4 SRAM Instance, M4S12~M4S15. This bit will be set if any of the Memories (M4S12~M4S15) been wakeup by Hardware."]
215pub type PATH_4_GATING_CONTROL_R = PATH_0_GATING_CONTROL_R;
216#[doc = "Field `Path_4_Gating_Control` writer - RWHC: To M4 SRAM Instance, M4S12~M4S15. This bit will be set if any of the Memories (M4S12~M4S15) been wakeup by Hardware."]
217pub struct PATH_4_GATING_CONTROL_W<'a> {
218    w: &'a mut W,
219}
220impl<'a> PATH_4_GATING_CONTROL_W<'a> {
221    #[doc = r"Writes `variant` to the field"]
222    #[inline(always)]
223    pub fn variant(self, variant: PATH_4_GATING_CONTROL_A) -> &'a mut W {
224        self.bit(variant.into())
225    }
226    #[doc = "Clock is stop"]
227    #[inline(always)]
228    pub fn stop(self) -> &'a mut W {
229        self.variant(PATH_4_GATING_CONTROL_A::STOP)
230    }
231    #[doc = "Clock is runnig"]
232    #[inline(always)]
233    pub fn run(self) -> &'a mut W {
234        self.variant(PATH_4_GATING_CONTROL_A::RUN)
235    }
236    #[doc = r"Sets the field bit"]
237    #[inline(always)]
238    pub fn set_bit(self) -> &'a mut W {
239        self.bit(true)
240    }
241    #[doc = r"Clears the field bit"]
242    #[inline(always)]
243    pub fn clear_bit(self) -> &'a mut W {
244        self.bit(false)
245    }
246    #[doc = r"Writes raw bits to the field"]
247    #[inline(always)]
248    pub fn bit(self, value: bool) -> &'a mut W {
249        self.w.bits =
250            (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
251        self.w
252    }
253}
254#[doc = "To AUDIO DMA"]
255pub type PATH_5_GATING_CONTROL_A = PATH_0_GATING_CONTROL_A;
256#[doc = "Field `Path_5_Gating_Control` reader - To AUDIO DMA"]
257pub type PATH_5_GATING_CONTROL_R = PATH_0_GATING_CONTROL_R;
258#[doc = "Field `Path_5_Gating_Control` writer - To AUDIO DMA"]
259pub struct PATH_5_GATING_CONTROL_W<'a> {
260    w: &'a mut W,
261}
262impl<'a> PATH_5_GATING_CONTROL_W<'a> {
263    #[doc = r"Writes `variant` to the field"]
264    #[inline(always)]
265    pub fn variant(self, variant: PATH_5_GATING_CONTROL_A) -> &'a mut W {
266        self.bit(variant.into())
267    }
268    #[doc = "Clock is stop"]
269    #[inline(always)]
270    pub fn stop(self) -> &'a mut W {
271        self.variant(PATH_5_GATING_CONTROL_A::STOP)
272    }
273    #[doc = "Clock is runnig"]
274    #[inline(always)]
275    pub fn run(self) -> &'a mut W {
276        self.variant(PATH_5_GATING_CONTROL_A::RUN)
277    }
278    #[doc = r"Sets the field bit"]
279    #[inline(always)]
280    pub fn set_bit(self) -> &'a mut W {
281        self.bit(true)
282    }
283    #[doc = r"Clears the field bit"]
284    #[inline(always)]
285    pub fn clear_bit(self) -> &'a mut W {
286        self.bit(false)
287    }
288    #[doc = r"Writes raw bits to the field"]
289    #[inline(always)]
290    pub fn bit(self, value: bool) -> &'a mut W {
291        self.w.bits =
292            (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
293        self.w
294    }
295}
296#[doc = "To the SYNC Up on A0 and AHB Interface of Batching Memory"]
297pub type PATH_6_GATING_CONTROL_A = PATH_0_GATING_CONTROL_A;
298#[doc = "Field `Path_6_Gating_Control` reader - To the SYNC Up on A0 and AHB Interface of Batching Memory"]
299pub type PATH_6_GATING_CONTROL_R = PATH_0_GATING_CONTROL_R;
300#[doc = "Field `Path_6_Gating_Control` writer - To the SYNC Up on A0 and AHB Interface of Batching Memory"]
301pub struct PATH_6_GATING_CONTROL_W<'a> {
302    w: &'a mut W,
303}
304impl<'a> PATH_6_GATING_CONTROL_W<'a> {
305    #[doc = r"Writes `variant` to the field"]
306    #[inline(always)]
307    pub fn variant(self, variant: PATH_6_GATING_CONTROL_A) -> &'a mut W {
308        self.bit(variant.into())
309    }
310    #[doc = "Clock is stop"]
311    #[inline(always)]
312    pub fn stop(self) -> &'a mut W {
313        self.variant(PATH_6_GATING_CONTROL_A::STOP)
314    }
315    #[doc = "Clock is runnig"]
316    #[inline(always)]
317    pub fn run(self) -> &'a mut W {
318        self.variant(PATH_6_GATING_CONTROL_A::RUN)
319    }
320    #[doc = r"Sets the field bit"]
321    #[inline(always)]
322    pub fn set_bit(self) -> &'a mut W {
323        self.bit(true)
324    }
325    #[doc = r"Clears the field bit"]
326    #[inline(always)]
327    pub fn clear_bit(self) -> &'a mut W {
328        self.bit(false)
329    }
330    #[doc = r"Writes raw bits to the field"]
331    #[inline(always)]
332    pub fn bit(self, value: bool) -> &'a mut W {
333        self.w.bits =
334            (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
335        self.w
336    }
337}
338impl R {
339    #[doc = "Bit 0 - To M4 Bus Matrix and Trace block"]
340    #[inline(always)]
341    pub fn path_0_gating_control(&self) -> PATH_0_GATING_CONTROL_R {
342        PATH_0_GATING_CONTROL_R::new((self.bits & 0x01) != 0)
343    }
344    #[doc = "Bit 1 - RWHC: To M4 SRAM Instance, M4S0~M4S3. This bit will be set if any of the Memories (M4S0~M4S3) been wakeup by Hardware."]
345    #[inline(always)]
346    pub fn path_1_gating_control(&self) -> PATH_1_GATING_CONTROL_R {
347        PATH_1_GATING_CONTROL_R::new(((self.bits >> 1) & 0x01) != 0)
348    }
349    #[doc = "Bit 2 - RWHC: To M4 SRAM Instance, M4S4~M4S7. This bit will be set if any of the Memories (M4S4~M4S7) been wakeup by Hardware."]
350    #[inline(always)]
351    pub fn path_2_gating_control(&self) -> PATH_2_GATING_CONTROL_R {
352        PATH_2_GATING_CONTROL_R::new(((self.bits >> 2) & 0x01) != 0)
353    }
354    #[doc = "Bit 3 - RWHC: To M4 SRAM Instance, M4S8~M4S11. This bit will be set if any of the Memories (M4S8~M4S11) been wakeup by Hardware."]
355    #[inline(always)]
356    pub fn path_3_gating_control(&self) -> PATH_3_GATING_CONTROL_R {
357        PATH_3_GATING_CONTROL_R::new(((self.bits >> 3) & 0x01) != 0)
358    }
359    #[doc = "Bit 4 - RWHC: To M4 SRAM Instance, M4S12~M4S15. This bit will be set if any of the Memories (M4S12~M4S15) been wakeup by Hardware."]
360    #[inline(always)]
361    pub fn path_4_gating_control(&self) -> PATH_4_GATING_CONTROL_R {
362        PATH_4_GATING_CONTROL_R::new(((self.bits >> 4) & 0x01) != 0)
363    }
364    #[doc = "Bit 5 - To AUDIO DMA"]
365    #[inline(always)]
366    pub fn path_5_gating_control(&self) -> PATH_5_GATING_CONTROL_R {
367        PATH_5_GATING_CONTROL_R::new(((self.bits >> 5) & 0x01) != 0)
368    }
369    #[doc = "Bit 6 - To the SYNC Up on A0 and AHB Interface of Batching Memory"]
370    #[inline(always)]
371    pub fn path_6_gating_control(&self) -> PATH_6_GATING_CONTROL_R {
372        PATH_6_GATING_CONTROL_R::new(((self.bits >> 6) & 0x01) != 0)
373    }
374}
375impl W {
376    #[doc = "Bit 1 - RWHC: To M4 SRAM Instance, M4S0~M4S3. This bit will be set if any of the Memories (M4S0~M4S3) been wakeup by Hardware."]
377    #[inline(always)]
378    pub fn path_1_gating_control(&mut self) -> PATH_1_GATING_CONTROL_W {
379        PATH_1_GATING_CONTROL_W { w: self }
380    }
381    #[doc = "Bit 2 - RWHC: To M4 SRAM Instance, M4S4~M4S7. This bit will be set if any of the Memories (M4S4~M4S7) been wakeup by Hardware."]
382    #[inline(always)]
383    pub fn path_2_gating_control(&mut self) -> PATH_2_GATING_CONTROL_W {
384        PATH_2_GATING_CONTROL_W { w: self }
385    }
386    #[doc = "Bit 3 - RWHC: To M4 SRAM Instance, M4S8~M4S11. This bit will be set if any of the Memories (M4S8~M4S11) been wakeup by Hardware."]
387    #[inline(always)]
388    pub fn path_3_gating_control(&mut self) -> PATH_3_GATING_CONTROL_W {
389        PATH_3_GATING_CONTROL_W { w: self }
390    }
391    #[doc = "Bit 4 - RWHC: To M4 SRAM Instance, M4S12~M4S15. This bit will be set if any of the Memories (M4S12~M4S15) been wakeup by Hardware."]
392    #[inline(always)]
393    pub fn path_4_gating_control(&mut self) -> PATH_4_GATING_CONTROL_W {
394        PATH_4_GATING_CONTROL_W { w: self }
395    }
396    #[doc = "Bit 5 - To AUDIO DMA"]
397    #[inline(always)]
398    pub fn path_5_gating_control(&mut self) -> PATH_5_GATING_CONTROL_W {
399        PATH_5_GATING_CONTROL_W { w: self }
400    }
401    #[doc = "Bit 6 - To the SYNC Up on A0 and AHB Interface of Batching Memory"]
402    #[inline(always)]
403    pub fn path_6_gating_control(&mut self) -> PATH_6_GATING_CONTROL_W {
404        PATH_6_GATING_CONTROL_W { w: self }
405    }
406    #[doc = "Writes raw bits to the register."]
407    #[inline(always)]
408    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
409        self.0.bits(bits);
410        self
411    }
412}
413#[doc = "Gating control for Clock 10\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c10_fclk_gate](index.html) module"]
414pub struct C10_FCLK_GATE_SPEC;
415impl crate::RegisterSpec for C10_FCLK_GATE_SPEC {
416    type Ux = u32;
417}
418#[doc = "`read()` method returns [c10_fclk_gate::R](R) reader structure"]
419impl crate::Readable for C10_FCLK_GATE_SPEC {
420    type Reader = R;
421}
422#[doc = "`write(|w| ..)` method takes [c10_fclk_gate::W](W) writer structure"]
423impl crate::Writable for C10_FCLK_GATE_SPEC {
424    type Writer = W;
425}
426#[doc = "`reset()` method sets C10_FCLK_GATE to value 0x43"]
427impl crate::Resettable for C10_FCLK_GATE_SPEC {
428    #[inline(always)]
429    fn reset_value() -> Self::Ux {
430        0x43
431    }
432}
eos_s3/cru/c10_fclk_gate.rs

eos_s3/cru/
c10_fclk_gate.rs
