eos_s3/cru/
c08_x1_clk_gate.rs

1#[doc = "Register `C08_X1_CLK_GATE` reader"]
2pub struct R(crate::R<C08_X1_CLK_GATE_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<C08_X1_CLK_GATE_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<C08_X1_CLK_GATE_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<C08_X1_CLK_GATE_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `C08_X1_CLK_GATE` writer"]
17pub struct W(crate::W<C08_X1_CLK_GATE_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<C08_X1_CLK_GATE_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<C08_X1_CLK_GATE_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<C08_X1_CLK_GATE_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "To FFE X1 clk\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum PATH_0_GATING_CONTROL_A {
40    #[doc = "0: Clock is stop"]
41    STOP = 0,
42    #[doc = "1: Clock is runnig"]
43    RUN = 1,
44}
45impl From<PATH_0_GATING_CONTROL_A> for bool {
46    #[inline(always)]
47    fn from(variant: PATH_0_GATING_CONTROL_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `Path_0_Gating_Control` reader - To FFE X1 clk"]
52pub struct PATH_0_GATING_CONTROL_R(
53    crate::FieldReader<bool, PATH_0_GATING_CONTROL_A>,
54);
55impl PATH_0_GATING_CONTROL_R {
56    #[inline(always)]
57    pub(crate) fn new(bits: bool) -> Self {
58        PATH_0_GATING_CONTROL_R(crate::FieldReader::new(bits))
59    }
60    #[doc = r"Get enumerated values variant"]
61    #[inline(always)]
62    pub fn variant(&self) -> PATH_0_GATING_CONTROL_A {
63        match self.bits {
64            false => PATH_0_GATING_CONTROL_A::STOP,
65            true => PATH_0_GATING_CONTROL_A::RUN,
66        }
67    }
68    #[doc = "Checks if the value of the field is `STOP`"]
69    #[inline(always)]
70    pub fn is_stop(&self) -> bool {
71        **self == PATH_0_GATING_CONTROL_A::STOP
72    }
73    #[doc = "Checks if the value of the field is `RUN`"]
74    #[inline(always)]
75    pub fn is_run(&self) -> bool {
76        **self == PATH_0_GATING_CONTROL_A::RUN
77    }
78}
79impl core::ops::Deref for PATH_0_GATING_CONTROL_R {
80    type Target = crate::FieldReader<bool, PATH_0_GATING_CONTROL_A>;
81    #[inline(always)]
82    fn deref(&self) -> &Self::Target {
83        &self.0
84    }
85}
86#[doc = "Field `Path_0_Gating_Control` writer - To FFE X1 clk"]
87pub struct PATH_0_GATING_CONTROL_W<'a> {
88    w: &'a mut W,
89}
90impl<'a> PATH_0_GATING_CONTROL_W<'a> {
91    #[doc = r"Writes `variant` to the field"]
92    #[inline(always)]
93    pub fn variant(self, variant: PATH_0_GATING_CONTROL_A) -> &'a mut W {
94        self.bit(variant.into())
95    }
96    #[doc = "Clock is stop"]
97    #[inline(always)]
98    pub fn stop(self) -> &'a mut W {
99        self.variant(PATH_0_GATING_CONTROL_A::STOP)
100    }
101    #[doc = "Clock is runnig"]
102    #[inline(always)]
103    pub fn run(self) -> &'a mut W {
104        self.variant(PATH_0_GATING_CONTROL_A::RUN)
105    }
106    #[doc = r"Sets the field bit"]
107    #[inline(always)]
108    pub fn set_bit(self) -> &'a mut W {
109        self.bit(true)
110    }
111    #[doc = r"Clears the field bit"]
112    #[inline(always)]
113    pub fn clear_bit(self) -> &'a mut W {
114        self.bit(false)
115    }
116    #[doc = r"Writes raw bits to the field"]
117    #[inline(always)]
118    pub fn bit(self, value: bool) -> &'a mut W {
119        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
120        self.w
121    }
122}
123#[doc = "To To A0"]
124pub type PATH_2_GATING_CONTROL_A = PATH_0_GATING_CONTROL_A;
125#[doc = "Field `Path_2_Gating_Control` reader - To To A0"]
126pub type PATH_2_GATING_CONTROL_R = PATH_0_GATING_CONTROL_R;
127#[doc = "Field `Path_2_Gating_Control` writer - To To A0"]
128pub struct PATH_2_GATING_CONTROL_W<'a> {
129    w: &'a mut W,
130}
131impl<'a> PATH_2_GATING_CONTROL_W<'a> {
132    #[doc = r"Writes `variant` to the field"]
133    #[inline(always)]
134    pub fn variant(self, variant: PATH_2_GATING_CONTROL_A) -> &'a mut W {
135        self.bit(variant.into())
136    }
137    #[doc = "Clock is stop"]
138    #[inline(always)]
139    pub fn stop(self) -> &'a mut W {
140        self.variant(PATH_2_GATING_CONTROL_A::STOP)
141    }
142    #[doc = "Clock is runnig"]
143    #[inline(always)]
144    pub fn run(self) -> &'a mut W {
145        self.variant(PATH_2_GATING_CONTROL_A::RUN)
146    }
147    #[doc = r"Sets the field bit"]
148    #[inline(always)]
149    pub fn set_bit(self) -> &'a mut W {
150        self.bit(true)
151    }
152    #[doc = r"Clears the field bit"]
153    #[inline(always)]
154    pub fn clear_bit(self) -> &'a mut W {
155        self.bit(false)
156    }
157    #[doc = r"Writes raw bits to the field"]
158    #[inline(always)]
159    pub fn bit(self, value: bool) -> &'a mut W {
160        self.w.bits =
161            (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
162        self.w
163    }
164}
165#[doc = "To To PF ASYNC FIFO 0"]
166pub type PATH_3_GATING_CONTROL_A = PATH_0_GATING_CONTROL_A;
167#[doc = "Field `Path_3_Gating_Control` reader - To To PF ASYNC FIFO 0"]
168pub type PATH_3_GATING_CONTROL_R = PATH_0_GATING_CONTROL_R;
169#[doc = "Field `Path_3_Gating_Control` writer - To To PF ASYNC FIFO 0"]
170pub struct PATH_3_GATING_CONTROL_W<'a> {
171    w: &'a mut W,
172}
173impl<'a> PATH_3_GATING_CONTROL_W<'a> {
174    #[doc = r"Writes `variant` to the field"]
175    #[inline(always)]
176    pub fn variant(self, variant: PATH_3_GATING_CONTROL_A) -> &'a mut W {
177        self.bit(variant.into())
178    }
179    #[doc = "Clock is stop"]
180    #[inline(always)]
181    pub fn stop(self) -> &'a mut W {
182        self.variant(PATH_3_GATING_CONTROL_A::STOP)
183    }
184    #[doc = "Clock is runnig"]
185    #[inline(always)]
186    pub fn run(self) -> &'a mut W {
187        self.variant(PATH_3_GATING_CONTROL_A::RUN)
188    }
189    #[doc = r"Sets the field bit"]
190    #[inline(always)]
191    pub fn set_bit(self) -> &'a mut W {
192        self.bit(true)
193    }
194    #[doc = r"Clears the field bit"]
195    #[inline(always)]
196    pub fn clear_bit(self) -> &'a mut W {
197        self.bit(false)
198    }
199    #[doc = r"Writes raw bits to the field"]
200    #[inline(always)]
201    pub fn bit(self, value: bool) -> &'a mut W {
202        self.w.bits =
203            (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
204        self.w
205    }
206}
207impl R {
208    #[doc = "Bit 0 - To FFE X1 clk"]
209    #[inline(always)]
210    pub fn path_0_gating_control(&self) -> PATH_0_GATING_CONTROL_R {
211        PATH_0_GATING_CONTROL_R::new((self.bits & 0x01) != 0)
212    }
213    #[doc = "Bit 2 - To To A0"]
214    #[inline(always)]
215    pub fn path_2_gating_control(&self) -> PATH_2_GATING_CONTROL_R {
216        PATH_2_GATING_CONTROL_R::new(((self.bits >> 2) & 0x01) != 0)
217    }
218    #[doc = "Bit 3 - To To PF ASYNC FIFO 0"]
219    #[inline(always)]
220    pub fn path_3_gating_control(&self) -> PATH_3_GATING_CONTROL_R {
221        PATH_3_GATING_CONTROL_R::new(((self.bits >> 3) & 0x01) != 0)
222    }
223}
224impl W {
225    #[doc = "Bit 0 - To FFE X1 clk"]
226    #[inline(always)]
227    pub fn path_0_gating_control(&mut self) -> PATH_0_GATING_CONTROL_W {
228        PATH_0_GATING_CONTROL_W { w: self }
229    }
230    #[doc = "Bit 2 - To To A0"]
231    #[inline(always)]
232    pub fn path_2_gating_control(&mut self) -> PATH_2_GATING_CONTROL_W {
233        PATH_2_GATING_CONTROL_W { w: self }
234    }
235    #[doc = "Bit 3 - To To PF ASYNC FIFO 0"]
236    #[inline(always)]
237    pub fn path_3_gating_control(&mut self) -> PATH_3_GATING_CONTROL_W {
238        PATH_3_GATING_CONTROL_W { w: self }
239    }
240    #[doc = "Writes raw bits to the register."]
241    #[inline(always)]
242    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
243        self.0.bits(bits);
244        self
245    }
246}
247#[doc = "Gating control for FFE X1 clock\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c08_x1_clk_gate](index.html) module"]
248pub struct C08_X1_CLK_GATE_SPEC;
249impl crate::RegisterSpec for C08_X1_CLK_GATE_SPEC {
250    type Ux = u32;
251}
252#[doc = "`read()` method returns [c08_x1_clk_gate::R](R) reader structure"]
253impl crate::Readable for C08_X1_CLK_GATE_SPEC {
254    type Reader = R;
255}
256#[doc = "`write(|w| ..)` method takes [c08_x1_clk_gate::W](W) writer structure"]
257impl crate::Writable for C08_X1_CLK_GATE_SPEC {
258    type Writer = W;
259}
260#[doc = "`reset()` method sets C08_X1_CLK_GATE to value 0"]
261impl crate::Resettable for C08_X1_CLK_GATE_SPEC {
262    #[inline(always)]
263    fn reset_value() -> Self::Ux {
264        0
265    }
266}
eos_s3/cru/c08_x1_clk_gate.rs

eos_s3/cru/
c08_x1_clk_gate.rs
