eos_s3/cru/
c01_clk_div.rs

1#[doc = "Register `C01_CLK_DIV` reader"]
2pub struct R(crate::R<C01_CLK_DIV_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<C01_CLK_DIV_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<C01_CLK_DIV_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<C01_CLK_DIV_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `C01_CLK_DIV` writer"]
17pub struct W(crate::W<C01_CLK_DIV_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<C01_CLK_DIV_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<C01_CLK_DIV_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<C01_CLK_DIV_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `C01_CLK_DIV` reader - The input clock frequency will be divided and generate the corresponding clock output. div is reg value + 1"]
38pub struct C01_CLK_DIV_R(crate::FieldReader<u8, u8>);
39impl C01_CLK_DIV_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: u8) -> Self {
42        C01_CLK_DIV_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for C01_CLK_DIV_R {
46    type Target = crate::FieldReader<u8, u8>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `C01_CLK_DIV` writer - The input clock frequency will be divided and generate the corresponding clock output. div is reg value + 1"]
53pub struct C01_CLK_DIV_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> C01_CLK_DIV_W<'a> {
57    #[doc = r"Writes raw bits to the field"]
58    #[inline(always)]
59    pub unsafe fn bits(self, value: u8) -> &'a mut W {
60        self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f);
61        self.w
62    }
63}
64#[doc = "This bit is used to turn off the clock for the SYNC down Divider\n\nValue on reset: 1"]
65#[derive(Clone, Copy, Debug, PartialEq)]
66pub enum C01_CLK_DIV_CG_A {
67    #[doc = "0: Clock is stop"]
68    STOP = 0,
69    #[doc = "1: Clock is runnig"]
70    RUN = 1,
71}
72impl From<C01_CLK_DIV_CG_A> for bool {
73    #[inline(always)]
74    fn from(variant: C01_CLK_DIV_CG_A) -> Self {
75        variant as u8 != 0
76    }
77}
78#[doc = "Field `C01_CLK_DIV_CG` reader - This bit is used to turn off the clock for the SYNC down Divider"]
79pub struct C01_CLK_DIV_CG_R(crate::FieldReader<bool, C01_CLK_DIV_CG_A>);
80impl C01_CLK_DIV_CG_R {
81    #[inline(always)]
82    pub(crate) fn new(bits: bool) -> Self {
83        C01_CLK_DIV_CG_R(crate::FieldReader::new(bits))
84    }
85    #[doc = r"Get enumerated values variant"]
86    #[inline(always)]
87    pub fn variant(&self) -> C01_CLK_DIV_CG_A {
88        match self.bits {
89            false => C01_CLK_DIV_CG_A::STOP,
90            true => C01_CLK_DIV_CG_A::RUN,
91        }
92    }
93    #[doc = "Checks if the value of the field is `STOP`"]
94    #[inline(always)]
95    pub fn is_stop(&self) -> bool {
96        **self == C01_CLK_DIV_CG_A::STOP
97    }
98    #[doc = "Checks if the value of the field is `RUN`"]
99    #[inline(always)]
100    pub fn is_run(&self) -> bool {
101        **self == C01_CLK_DIV_CG_A::RUN
102    }
103}
104impl core::ops::Deref for C01_CLK_DIV_CG_R {
105    type Target = crate::FieldReader<bool, C01_CLK_DIV_CG_A>;
106    #[inline(always)]
107    fn deref(&self) -> &Self::Target {
108        &self.0
109    }
110}
111#[doc = "Field `C01_CLK_DIV_CG` writer - This bit is used to turn off the clock for the SYNC down Divider"]
112pub struct C01_CLK_DIV_CG_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> C01_CLK_DIV_CG_W<'a> {
116    #[doc = r"Writes `variant` to the field"]
117    #[inline(always)]
118    pub fn variant(self, variant: C01_CLK_DIV_CG_A) -> &'a mut W {
119        self.bit(variant.into())
120    }
121    #[doc = "Clock is stop"]
122    #[inline(always)]
123    pub fn stop(self) -> &'a mut W {
124        self.variant(C01_CLK_DIV_CG_A::STOP)
125    }
126    #[doc = "Clock is runnig"]
127    #[inline(always)]
128    pub fn run(self) -> &'a mut W {
129        self.variant(C01_CLK_DIV_CG_A::RUN)
130    }
131    #[doc = r"Sets the field bit"]
132    #[inline(always)]
133    pub fn set_bit(self) -> &'a mut W {
134        self.bit(true)
135    }
136    #[doc = r"Clears the field bit"]
137    #[inline(always)]
138    pub fn clear_bit(self) -> &'a mut W {
139        self.bit(false)
140    }
141    #[doc = r"Writes raw bits to the field"]
142    #[inline(always)]
143    pub fn bit(self, value: bool) -> &'a mut W {
144        self.w.bits =
145            (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
146        self.w
147    }
148}
149impl R {
150    #[doc = "Bits 0:3 - The input clock frequency will be divided and generate the corresponding clock output. div is reg value + 1"]
151    #[inline(always)]
152    pub fn c01_clk_div(&self) -> C01_CLK_DIV_R {
153        C01_CLK_DIV_R::new((self.bits & 0x0f) as u8)
154    }
155    #[doc = "Bit 4 - This bit is used to turn off the clock for the SYNC down Divider"]
156    #[inline(always)]
157    pub fn c01_clk_div_cg(&self) -> C01_CLK_DIV_CG_R {
158        C01_CLK_DIV_CG_R::new(((self.bits >> 4) & 0x01) != 0)
159    }
160}
161impl W {
162    #[doc = "Bits 0:3 - The input clock frequency will be divided and generate the corresponding clock output. div is reg value + 1"]
163    #[inline(always)]
164    pub fn c01_clk_div(&mut self) -> C01_CLK_DIV_W {
165        C01_CLK_DIV_W { w: self }
166    }
167    #[doc = "Bit 4 - This bit is used to turn off the clock for the SYNC down Divider"]
168    #[inline(always)]
169    pub fn c01_clk_div_cg(&mut self) -> C01_CLK_DIV_CG_W {
170        C01_CLK_DIV_CG_W { w: self }
171    }
172    #[doc = "Writes raw bits to the register."]
173    #[inline(always)]
174    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
175        self.0.bits(bits);
176        self
177    }
178}
179#[doc = "Source Clock is C10 (CLK to SDMA,I2S module Inside A1, AHB2APB Bridge /CFG DMA Bridge inside A1 , FFE, Packet FIFO,SDMA,A0 ) If Bit 4 is 0, any change on Bit 3:0 will not take effect. And bit 4 and bit 3:0 can not change at same time.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c01_clk_div](index.html) module"]
180pub struct C01_CLK_DIV_SPEC;
181impl crate::RegisterSpec for C01_CLK_DIV_SPEC {
182    type Ux = u32;
183}
184#[doc = "`read()` method returns [c01_clk_div::R](R) reader structure"]
185impl crate::Readable for C01_CLK_DIV_SPEC {
186    type Reader = R;
187}
188#[doc = "`write(|w| ..)` method takes [c01_clk_div::W](W) writer structure"]
189impl crate::Writable for C01_CLK_DIV_SPEC {
190    type Writer = W;
191}
192#[doc = "`reset()` method sets C01_CLK_DIV to value 0x11"]
193impl crate::Resettable for C01_CLK_DIV_SPEC {
194    #[inline(always)]
195    fn reset_value() -> Self::Ux {
196        0x11
197    }
198}
eos_s3/cru/c01_clk_div.rs

eos_s3/cru/
c01_clk_div.rs
