eos_s3/cru/
audio_misc_sw_reset.rs

1#[doc = "Register `AUDIO_MISC_SW_RESET` reader"]
2pub struct R(crate::R<AUDIO_MISC_SW_RESET_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<AUDIO_MISC_SW_RESET_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<AUDIO_MISC_SW_RESET_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<AUDIO_MISC_SW_RESET_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `AUDIO_MISC_SW_RESET` writer"]
17pub struct W(crate::W<AUDIO_MISC_SW_RESET_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<AUDIO_MISC_SW_RESET_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<AUDIO_MISC_SW_RESET_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<AUDIO_MISC_SW_RESET_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum AD0_SW_RESET_A {
40    #[doc = "1: Enable the software reset. FW need to disable it manually"]
41    ENABLE = 1,
42}
43impl From<AD0_SW_RESET_A> for bool {
44    #[inline(always)]
45    fn from(variant: AD0_SW_RESET_A) -> Self {
46        variant as u8 != 0
47    }
48}
49#[doc = "Field `AD0_SW_RESET` reader - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
50pub struct AD0_SW_RESET_R(crate::FieldReader<bool, AD0_SW_RESET_A>);
51impl AD0_SW_RESET_R {
52    #[inline(always)]
53    pub(crate) fn new(bits: bool) -> Self {
54        AD0_SW_RESET_R(crate::FieldReader::new(bits))
55    }
56    #[doc = r"Get enumerated values variant"]
57    #[inline(always)]
58    pub fn variant(&self) -> Option<AD0_SW_RESET_A> {
59        match self.bits {
60            true => Some(AD0_SW_RESET_A::ENABLE),
61            _ => None,
62        }
63    }
64    #[doc = "Checks if the value of the field is `ENABLE`"]
65    #[inline(always)]
66    pub fn is_enable(&self) -> bool {
67        **self == AD0_SW_RESET_A::ENABLE
68    }
69}
70impl core::ops::Deref for AD0_SW_RESET_R {
71    type Target = crate::FieldReader<bool, AD0_SW_RESET_A>;
72    #[inline(always)]
73    fn deref(&self) -> &Self::Target {
74        &self.0
75    }
76}
77#[doc = "Field `AD0_SW_RESET` writer - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
78pub struct AD0_SW_RESET_W<'a> {
79    w: &'a mut W,
80}
81impl<'a> AD0_SW_RESET_W<'a> {
82    #[doc = r"Writes `variant` to the field"]
83    #[inline(always)]
84    pub fn variant(self, variant: AD0_SW_RESET_A) -> &'a mut W {
85        self.bit(variant.into())
86    }
87    #[doc = "Enable the software reset. FW need to disable it manually"]
88    #[inline(always)]
89    pub fn enable(self) -> &'a mut W {
90        self.variant(AD0_SW_RESET_A::ENABLE)
91    }
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
106        self.w
107    }
108}
109#[doc = "1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
110pub type AD1_SW_RESET_A = AD0_SW_RESET_A;
111#[doc = "Field `AD1_SW_RESET` reader - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
112pub type AD1_SW_RESET_R = AD0_SW_RESET_R;
113#[doc = "Field `AD1_SW_RESET` writer - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
114pub struct AD1_SW_RESET_W<'a> {
115    w: &'a mut W,
116}
117impl<'a> AD1_SW_RESET_W<'a> {
118    #[doc = r"Writes `variant` to the field"]
119    #[inline(always)]
120    pub fn variant(self, variant: AD1_SW_RESET_A) -> &'a mut W {
121        self.bit(variant.into())
122    }
123    #[doc = "Enable the software reset. FW need to disable it manually"]
124    #[inline(always)]
125    pub fn enable(self) -> &'a mut W {
126        self.variant(AD1_SW_RESET_A::ENABLE)
127    }
128    #[doc = r"Sets the field bit"]
129    #[inline(always)]
130    pub fn set_bit(self) -> &'a mut W {
131        self.bit(true)
132    }
133    #[doc = r"Clears the field bit"]
134    #[inline(always)]
135    pub fn clear_bit(self) -> &'a mut W {
136        self.bit(false)
137    }
138    #[doc = r"Writes raw bits to the field"]
139    #[inline(always)]
140    pub fn bit(self, value: bool) -> &'a mut W {
141        self.w.bits =
142            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
143        self.w
144    }
145}
146#[doc = "1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
147pub type AD2_SW_RESET_A = AD0_SW_RESET_A;
148#[doc = "Field `AD2_SW_RESET` reader - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
149pub type AD2_SW_RESET_R = AD0_SW_RESET_R;
150#[doc = "Field `AD2_SW_RESET` writer - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
151pub struct AD2_SW_RESET_W<'a> {
152    w: &'a mut W,
153}
154impl<'a> AD2_SW_RESET_W<'a> {
155    #[doc = r"Writes `variant` to the field"]
156    #[inline(always)]
157    pub fn variant(self, variant: AD2_SW_RESET_A) -> &'a mut W {
158        self.bit(variant.into())
159    }
160    #[doc = "Enable the software reset. FW need to disable it manually"]
161    #[inline(always)]
162    pub fn enable(self) -> &'a mut W {
163        self.variant(AD2_SW_RESET_A::ENABLE)
164    }
165    #[doc = r"Sets the field bit"]
166    #[inline(always)]
167    pub fn set_bit(self) -> &'a mut W {
168        self.bit(true)
169    }
170    #[doc = r"Clears the field bit"]
171    #[inline(always)]
172    pub fn clear_bit(self) -> &'a mut W {
173        self.bit(false)
174    }
175    #[doc = r"Writes raw bits to the field"]
176    #[inline(always)]
177    pub fn bit(self, value: bool) -> &'a mut W {
178        self.w.bits =
179            (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
180        self.w
181    }
182}
183#[doc = "1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
184pub type AD3_SW_RESET_A = AD0_SW_RESET_A;
185#[doc = "Field `AD3_SW_RESET` reader - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
186pub type AD3_SW_RESET_R = AD0_SW_RESET_R;
187#[doc = "Field `AD3_SW_RESET` writer - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
188pub struct AD3_SW_RESET_W<'a> {
189    w: &'a mut W,
190}
191impl<'a> AD3_SW_RESET_W<'a> {
192    #[doc = r"Writes `variant` to the field"]
193    #[inline(always)]
194    pub fn variant(self, variant: AD3_SW_RESET_A) -> &'a mut W {
195        self.bit(variant.into())
196    }
197    #[doc = "Enable the software reset. FW need to disable it manually"]
198    #[inline(always)]
199    pub fn enable(self) -> &'a mut W {
200        self.variant(AD3_SW_RESET_A::ENABLE)
201    }
202    #[doc = r"Sets the field bit"]
203    #[inline(always)]
204    pub fn set_bit(self) -> &'a mut W {
205        self.bit(true)
206    }
207    #[doc = r"Clears the field bit"]
208    #[inline(always)]
209    pub fn clear_bit(self) -> &'a mut W {
210        self.bit(false)
211    }
212    #[doc = r"Writes raw bits to the field"]
213    #[inline(always)]
214    pub fn bit(self, value: bool) -> &'a mut W {
215        self.w.bits =
216            (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
217        self.w
218    }
219}
220#[doc = "1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
221pub type AD4_SW_RESET_A = AD0_SW_RESET_A;
222#[doc = "Field `AD4_SW_RESET` reader - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
223pub type AD4_SW_RESET_R = AD0_SW_RESET_R;
224#[doc = "Field `AD4_SW_RESET` writer - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
225pub struct AD4_SW_RESET_W<'a> {
226    w: &'a mut W,
227}
228impl<'a> AD4_SW_RESET_W<'a> {
229    #[doc = r"Writes `variant` to the field"]
230    #[inline(always)]
231    pub fn variant(self, variant: AD4_SW_RESET_A) -> &'a mut W {
232        self.bit(variant.into())
233    }
234    #[doc = "Enable the software reset. FW need to disable it manually"]
235    #[inline(always)]
236    pub fn enable(self) -> &'a mut W {
237        self.variant(AD4_SW_RESET_A::ENABLE)
238    }
239    #[doc = r"Sets the field bit"]
240    #[inline(always)]
241    pub fn set_bit(self) -> &'a mut W {
242        self.bit(true)
243    }
244    #[doc = r"Clears the field bit"]
245    #[inline(always)]
246    pub fn clear_bit(self) -> &'a mut W {
247        self.bit(false)
248    }
249    #[doc = r"Writes raw bits to the field"]
250    #[inline(always)]
251    pub fn bit(self, value: bool) -> &'a mut W {
252        self.w.bits =
253            (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
254        self.w
255    }
256}
257#[doc = "1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
258pub type AD5_SW_RESET_A = AD0_SW_RESET_A;
259#[doc = "Field `AD5_SW_RESET` reader - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
260pub type AD5_SW_RESET_R = AD0_SW_RESET_R;
261#[doc = "Field `AD5_SW_RESET` writer - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
262pub struct AD5_SW_RESET_W<'a> {
263    w: &'a mut W,
264}
265impl<'a> AD5_SW_RESET_W<'a> {
266    #[doc = r"Writes `variant` to the field"]
267    #[inline(always)]
268    pub fn variant(self, variant: AD5_SW_RESET_A) -> &'a mut W {
269        self.bit(variant.into())
270    }
271    #[doc = "Enable the software reset. FW need to disable it manually"]
272    #[inline(always)]
273    pub fn enable(self) -> &'a mut W {
274        self.variant(AD5_SW_RESET_A::ENABLE)
275    }
276    #[doc = r"Sets the field bit"]
277    #[inline(always)]
278    pub fn set_bit(self) -> &'a mut W {
279        self.bit(true)
280    }
281    #[doc = r"Clears the field bit"]
282    #[inline(always)]
283    pub fn clear_bit(self) -> &'a mut W {
284        self.bit(false)
285    }
286    #[doc = r"Writes raw bits to the field"]
287    #[inline(always)]
288    pub fn bit(self, value: bool) -> &'a mut W {
289        self.w.bits =
290            (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
291        self.w
292    }
293}
294#[doc = "1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
295pub type DMA_SW_RESET_A = AD0_SW_RESET_A;
296#[doc = "Field `DMA_SW_RESET` reader - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
297pub type DMA_SW_RESET_R = AD0_SW_RESET_R;
298#[doc = "Field `DMA_SW_RESET` writer - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
299pub struct DMA_SW_RESET_W<'a> {
300    w: &'a mut W,
301}
302impl<'a> DMA_SW_RESET_W<'a> {
303    #[doc = r"Writes `variant` to the field"]
304    #[inline(always)]
305    pub fn variant(self, variant: DMA_SW_RESET_A) -> &'a mut W {
306        self.bit(variant.into())
307    }
308    #[doc = "Enable the software reset. FW need to disable it manually"]
309    #[inline(always)]
310    pub fn enable(self) -> &'a mut W {
311        self.variant(DMA_SW_RESET_A::ENABLE)
312    }
313    #[doc = r"Sets the field bit"]
314    #[inline(always)]
315    pub fn set_bit(self) -> &'a mut W {
316        self.bit(true)
317    }
318    #[doc = r"Clears the field bit"]
319    #[inline(always)]
320    pub fn clear_bit(self) -> &'a mut W {
321        self.bit(false)
322    }
323    #[doc = r"Writes raw bits to the field"]
324    #[inline(always)]
325    pub fn bit(self, value: bool) -> &'a mut W {
326        self.w.bits =
327            (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
328        self.w
329    }
330}
331#[doc = "1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For I2S Power Domain. Note: It will only reset the AHB interface R01, but it will not reset R32 path. Suggest to power down, then power on I2S if Software Reset is needed"]
332pub type I2S_SW_RESET_A = AD0_SW_RESET_A;
333#[doc = "Field `I2S_SW_RESET` reader - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For I2S Power Domain. Note: It will only reset the AHB interface R01, but it will not reset R32 path. Suggest to power down, then power on I2S if Software Reset is needed"]
334pub type I2S_SW_RESET_R = AD0_SW_RESET_R;
335#[doc = "Field `I2S_SW_RESET` writer - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For I2S Power Domain. Note: It will only reset the AHB interface R01, but it will not reset R32 path. Suggest to power down, then power on I2S if Software Reset is needed"]
336pub struct I2S_SW_RESET_W<'a> {
337    w: &'a mut W,
338}
339impl<'a> I2S_SW_RESET_W<'a> {
340    #[doc = r"Writes `variant` to the field"]
341    #[inline(always)]
342    pub fn variant(self, variant: I2S_SW_RESET_A) -> &'a mut W {
343        self.bit(variant.into())
344    }
345    #[doc = "Enable the software reset. FW need to disable it manually"]
346    #[inline(always)]
347    pub fn enable(self) -> &'a mut W {
348        self.variant(I2S_SW_RESET_A::ENABLE)
349    }
350    #[doc = r"Sets the field bit"]
351    #[inline(always)]
352    pub fn set_bit(self) -> &'a mut W {
353        self.bit(true)
354    }
355    #[doc = r"Clears the field bit"]
356    #[inline(always)]
357    pub fn clear_bit(self) -> &'a mut W {
358        self.bit(false)
359    }
360    #[doc = r"Writes raw bits to the field"]
361    #[inline(always)]
362    pub fn bit(self, value: bool) -> &'a mut W {
363        self.w.bits =
364            (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
365        self.w
366    }
367}
368impl R {
369    #[doc = "Bit 0 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
370    #[inline(always)]
371    pub fn ad0_sw_reset(&self) -> AD0_SW_RESET_R {
372        AD0_SW_RESET_R::new((self.bits & 0x01) != 0)
373    }
374    #[doc = "Bit 1 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
375    #[inline(always)]
376    pub fn ad1_sw_reset(&self) -> AD1_SW_RESET_R {
377        AD1_SW_RESET_R::new(((self.bits >> 1) & 0x01) != 0)
378    }
379    #[doc = "Bit 2 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
380    #[inline(always)]
381    pub fn ad2_sw_reset(&self) -> AD2_SW_RESET_R {
382        AD2_SW_RESET_R::new(((self.bits >> 2) & 0x01) != 0)
383    }
384    #[doc = "Bit 3 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
385    #[inline(always)]
386    pub fn ad3_sw_reset(&self) -> AD3_SW_RESET_R {
387        AD3_SW_RESET_R::new(((self.bits >> 3) & 0x01) != 0)
388    }
389    #[doc = "Bit 4 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
390    #[inline(always)]
391    pub fn ad4_sw_reset(&self) -> AD4_SW_RESET_R {
392        AD4_SW_RESET_R::new(((self.bits >> 4) & 0x01) != 0)
393    }
394    #[doc = "Bit 5 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
395    #[inline(always)]
396    pub fn ad5_sw_reset(&self) -> AD5_SW_RESET_R {
397        AD5_SW_RESET_R::new(((self.bits >> 5) & 0x01) != 0)
398    }
399    #[doc = "Bit 6 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
400    #[inline(always)]
401    pub fn dma_sw_reset(&self) -> DMA_SW_RESET_R {
402        DMA_SW_RESET_R::new(((self.bits >> 6) & 0x01) != 0)
403    }
404    #[doc = "Bit 7 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For I2S Power Domain. Note: It will only reset the AHB interface R01, but it will not reset R32 path. Suggest to power down, then power on I2S if Software Reset is needed"]
405    #[inline(always)]
406    pub fn i2s_sw_reset(&self) -> I2S_SW_RESET_R {
407        I2S_SW_RESET_R::new(((self.bits >> 7) & 0x01) != 0)
408    }
409}
410impl W {
411    #[doc = "Bit 0 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
412    #[inline(always)]
413    pub fn ad0_sw_reset(&mut self) -> AD0_SW_RESET_W {
414        AD0_SW_RESET_W { w: self }
415    }
416    #[doc = "Bit 1 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
417    #[inline(always)]
418    pub fn ad1_sw_reset(&mut self) -> AD1_SW_RESET_W {
419        AD1_SW_RESET_W { w: self }
420    }
421    #[doc = "Bit 2 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
422    #[inline(always)]
423    pub fn ad2_sw_reset(&mut self) -> AD2_SW_RESET_W {
424        AD2_SW_RESET_W { w: self }
425    }
426    #[doc = "Bit 3 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
427    #[inline(always)]
428    pub fn ad3_sw_reset(&mut self) -> AD3_SW_RESET_W {
429        AD3_SW_RESET_W { w: self }
430    }
431    #[doc = "Bit 4 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
432    #[inline(always)]
433    pub fn ad4_sw_reset(&mut self) -> AD4_SW_RESET_W {
434        AD4_SW_RESET_W { w: self }
435    }
436    #[doc = "Bit 5 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
437    #[inline(always)]
438    pub fn ad5_sw_reset(&mut self) -> AD5_SW_RESET_W {
439        AD5_SW_RESET_W { w: self }
440    }
441    #[doc = "Bit 6 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For DMA Power Domain."]
442    #[inline(always)]
443    pub fn dma_sw_reset(&mut self) -> DMA_SW_RESET_W {
444        DMA_SW_RESET_W { w: self }
445    }
446    #[doc = "Bit 7 - 1'b1 : Enable the Software Reset. FW need to disable it manually. ==> For I2S Power Domain. Note: It will only reset the AHB interface R01, but it will not reset R32 path. Suggest to power down, then power on I2S if Software Reset is needed"]
447    #[inline(always)]
448    pub fn i2s_sw_reset(&mut self) -> I2S_SW_RESET_W {
449        I2S_SW_RESET_W { w: self }
450    }
451    #[doc = "Writes raw bits to the register."]
452    #[inline(always)]
453    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
454        self.0.bits(bits);
455        self
456    }
457}
458#[doc = "Once Program the SW Reset Bit to 1, the corresponding reset will be asserted immediately. Once Program the SW Reset Bit to 0, the corresponding reset will be de-asserted synchronous even the corresponding clock is not running. (Turn off by Clock gating cell)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [audio_misc_sw_reset](index.html) module"]
459pub struct AUDIO_MISC_SW_RESET_SPEC;
460impl crate::RegisterSpec for AUDIO_MISC_SW_RESET_SPEC {
461    type Ux = u32;
462}
463#[doc = "`read()` method returns [audio_misc_sw_reset::R](R) reader structure"]
464impl crate::Readable for AUDIO_MISC_SW_RESET_SPEC {
465    type Reader = R;
466}
467#[doc = "`write(|w| ..)` method takes [audio_misc_sw_reset::W](W) writer structure"]
468impl crate::Writable for AUDIO_MISC_SW_RESET_SPEC {
469    type Writer = W;
470}
471#[doc = "`reset()` method sets AUDIO_MISC_SW_RESET to value 0"]
472impl crate::Resettable for AUDIO_MISC_SW_RESET_SPEC {
473    #[inline(always)]
474    fn reset_value() -> Self::Ux {
475        0
476    }
477}
eos_s3/cru/audio_misc_sw_reset.rs

eos_s3/cru/
audio_misc_sw_reset.rs
