eos_s3/aud/
pdma_sram_cfg.rs

1#[doc = "Register `PDMA_SRAM_CFG` reader"]
2pub struct R(crate::R<PDMA_SRAM_CFG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PDMA_SRAM_CFG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PDMA_SRAM_CFG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PDMA_SRAM_CFG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PDMA_SRAM_CFG` writer"]
17pub struct W(crate::W<PDMA_SRAM_CFG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PDMA_SRAM_CFG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PDMA_SRAM_CFG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PDMA_SRAM_CFG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PDM_SRAM_L_TEST1` reader - Test pin to bypass self-timed circuit"]
38pub struct PDM_SRAM_L_TEST1_R(crate::FieldReader<bool, bool>);
39impl PDM_SRAM_L_TEST1_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: bool) -> Self {
42        PDM_SRAM_L_TEST1_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for PDM_SRAM_L_TEST1_R {
46    type Target = crate::FieldReader<bool, bool>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `PDM_SRAM_L_TEST1` writer - Test pin to bypass self-timed circuit"]
53pub struct PDM_SRAM_L_TEST1_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> PDM_SRAM_L_TEST1_W<'a> {
57    #[doc = r"Sets the field bit"]
58    #[inline(always)]
59    pub fn set_bit(self) -> &'a mut W {
60        self.bit(true)
61    }
62    #[doc = r"Clears the field bit"]
63    #[inline(always)]
64    pub fn clear_bit(self) -> &'a mut W {
65        self.bit(false)
66    }
67    #[doc = r"Writes raw bits to the field"]
68    #[inline(always)]
69    pub fn bit(self, value: bool) -> &'a mut W {
70        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
71        self.w
72    }
73}
74#[doc = "Field `PDM_SRAM_L_RME` reader - Read-Write margin Enable Input"]
75pub struct PDM_SRAM_L_RME_R(crate::FieldReader<bool, bool>);
76impl PDM_SRAM_L_RME_R {
77    #[inline(always)]
78    pub(crate) fn new(bits: bool) -> Self {
79        PDM_SRAM_L_RME_R(crate::FieldReader::new(bits))
80    }
81}
82impl core::ops::Deref for PDM_SRAM_L_RME_R {
83    type Target = crate::FieldReader<bool, bool>;
84    #[inline(always)]
85    fn deref(&self) -> &Self::Target {
86        &self.0
87    }
88}
89#[doc = "Field `PDM_SRAM_L_RME` writer - Read-Write margin Enable Input"]
90pub struct PDM_SRAM_L_RME_W<'a> {
91    w: &'a mut W,
92}
93impl<'a> PDM_SRAM_L_RME_W<'a> {
94    #[doc = r"Sets the field bit"]
95    #[inline(always)]
96    pub fn set_bit(self) -> &'a mut W {
97        self.bit(true)
98    }
99    #[doc = r"Clears the field bit"]
100    #[inline(always)]
101    pub fn clear_bit(self) -> &'a mut W {
102        self.bit(false)
103    }
104    #[doc = r"Writes raw bits to the field"]
105    #[inline(always)]
106    pub fn bit(self, value: bool) -> &'a mut W {
107        self.w.bits =
108            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
109        self.w
110    }
111}
112#[doc = "Field `PDM_SRAM_L_RM` reader - Read-Write margin Input for Right Channel PDM SRAM"]
113pub struct PDM_SRAM_L_RM_R(crate::FieldReader<u8, u8>);
114impl PDM_SRAM_L_RM_R {
115    #[inline(always)]
116    pub(crate) fn new(bits: u8) -> Self {
117        PDM_SRAM_L_RM_R(crate::FieldReader::new(bits))
118    }
119}
120impl core::ops::Deref for PDM_SRAM_L_RM_R {
121    type Target = crate::FieldReader<u8, u8>;
122    #[inline(always)]
123    fn deref(&self) -> &Self::Target {
124        &self.0
125    }
126}
127#[doc = "Field `PDM_SRAM_L_RM` writer - Read-Write margin Input for Right Channel PDM SRAM"]
128pub struct PDM_SRAM_L_RM_W<'a> {
129    w: &'a mut W,
130}
131impl<'a> PDM_SRAM_L_RM_W<'a> {
132    #[doc = r"Writes raw bits to the field"]
133    #[inline(always)]
134    pub unsafe fn bits(self, value: u8) -> &'a mut W {
135        self.w.bits =
136            (self.w.bits & !(0x0f << 2)) | ((value as u32 & 0x0f) << 2);
137        self.w
138    }
139}
140impl R {
141    #[doc = "Bit 0 - Test pin to bypass self-timed circuit"]
142    #[inline(always)]
143    pub fn pdm_sram_l_test1(&self) -> PDM_SRAM_L_TEST1_R {
144        PDM_SRAM_L_TEST1_R::new((self.bits & 0x01) != 0)
145    }
146    #[doc = "Bit 1 - Read-Write margin Enable Input"]
147    #[inline(always)]
148    pub fn pdm_sram_l_rme(&self) -> PDM_SRAM_L_RME_R {
149        PDM_SRAM_L_RME_R::new(((self.bits >> 1) & 0x01) != 0)
150    }
151    #[doc = "Bits 2:5 - Read-Write margin Input for Right Channel PDM SRAM"]
152    #[inline(always)]
153    pub fn pdm_sram_l_rm(&self) -> PDM_SRAM_L_RM_R {
154        PDM_SRAM_L_RM_R::new(((self.bits >> 2) & 0x0f) as u8)
155    }
156}
157impl W {
158    #[doc = "Bit 0 - Test pin to bypass self-timed circuit"]
159    #[inline(always)]
160    pub fn pdm_sram_l_test1(&mut self) -> PDM_SRAM_L_TEST1_W {
161        PDM_SRAM_L_TEST1_W { w: self }
162    }
163    #[doc = "Bit 1 - Read-Write margin Enable Input"]
164    #[inline(always)]
165    pub fn pdm_sram_l_rme(&mut self) -> PDM_SRAM_L_RME_W {
166        PDM_SRAM_L_RME_W { w: self }
167    }
168    #[doc = "Bits 2:5 - Read-Write margin Input for Right Channel PDM SRAM"]
169    #[inline(always)]
170    pub fn pdm_sram_l_rm(&mut self) -> PDM_SRAM_L_RM_W {
171        PDM_SRAM_L_RM_W { w: self }
172    }
173    #[doc = "Writes raw bits to the register."]
174    #[inline(always)]
175    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
176        self.0.bits(bits);
177        self
178    }
179}
180#[doc = "PDM core SRAM configure register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdma_sram_cfg](index.html) module"]
181pub struct PDMA_SRAM_CFG_SPEC;
182impl crate::RegisterSpec for PDMA_SRAM_CFG_SPEC {
183    type Ux = u32;
184}
185#[doc = "`read()` method returns [pdma_sram_cfg::R](R) reader structure"]
186impl crate::Readable for PDMA_SRAM_CFG_SPEC {
187    type Reader = R;
188}
189#[doc = "`write(|w| ..)` method takes [pdma_sram_cfg::W](W) writer structure"]
190impl crate::Writable for PDMA_SRAM_CFG_SPEC {
191    type Writer = W;
192}
193#[doc = "`reset()` method sets PDMA_SRAM_CFG to value 0"]
194impl crate::Resettable for PDMA_SRAM_CFG_SPEC {
195    #[inline(always)]
196    fn reset_value() -> Self::Ux {
197        0
198    }
199}
eos_s3/aud/pdma_sram_cfg.rs

eos_s3/aud/
pdma_sram_cfg.rs
