eos_s3/aud/
pdm_core_config.rs

1#[doc = "Register `PDM_CORE_CONFIG` reader"]
2pub struct R(crate::R<PDM_CORE_CONFIG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PDM_CORE_CONFIG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PDM_CORE_CONFIG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PDM_CORE_CONFIG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PDM_CORE_CONFIG` writer"]
17pub struct W(crate::W<PDM_CORE_CONFIG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PDM_CORE_CONFIG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PDM_CORE_CONFIG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PDM_CORE_CONFIG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PDM_CORE_CONFIG` reader - Set to enable PDM core"]
38pub struct PDM_CORE_CONFIG_R(crate::FieldReader<bool, bool>);
39impl PDM_CORE_CONFIG_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: bool) -> Self {
42        PDM_CORE_CONFIG_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for PDM_CORE_CONFIG_R {
46    type Target = crate::FieldReader<bool, bool>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `PDM_CORE_CONFIG` writer - Set to enable PDM core"]
53pub struct PDM_CORE_CONFIG_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> PDM_CORE_CONFIG_W<'a> {
57    #[doc = r"Sets the field bit"]
58    #[inline(always)]
59    pub fn set_bit(self) -> &'a mut W {
60        self.bit(true)
61    }
62    #[doc = r"Clears the field bit"]
63    #[inline(always)]
64    pub fn clear_bit(self) -> &'a mut W {
65        self.bit(false)
66    }
67    #[doc = r"Writes raw bits to the field"]
68    #[inline(always)]
69    pub fn bit(self, value: bool) -> &'a mut W {
70        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
71        self.w
72    }
73}
74#[doc = "Field `SOFT_MUTE` reader - Set to enable PDM Soft mute"]
75pub struct SOFT_MUTE_R(crate::FieldReader<bool, bool>);
76impl SOFT_MUTE_R {
77    #[inline(always)]
78    pub(crate) fn new(bits: bool) -> Self {
79        SOFT_MUTE_R(crate::FieldReader::new(bits))
80    }
81}
82impl core::ops::Deref for SOFT_MUTE_R {
83    type Target = crate::FieldReader<bool, bool>;
84    #[inline(always)]
85    fn deref(&self) -> &Self::Target {
86        &self.0
87    }
88}
89#[doc = "Field `SOFT_MUTE` writer - Set to enable PDM Soft mute"]
90pub struct SOFT_MUTE_W<'a> {
91    w: &'a mut W,
92}
93impl<'a> SOFT_MUTE_W<'a> {
94    #[doc = r"Sets the field bit"]
95    #[inline(always)]
96    pub fn set_bit(self) -> &'a mut W {
97        self.bit(true)
98    }
99    #[doc = r"Clears the field bit"]
100    #[inline(always)]
101    pub fn clear_bit(self) -> &'a mut W {
102        self.bit(false)
103    }
104    #[doc = r"Writes raw bits to the field"]
105    #[inline(always)]
106    pub fn bit(self, value: bool) -> &'a mut W {
107        self.w.bits =
108            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
109        self.w
110    }
111}
112#[doc = "Select which divider to use in sampler\n\nValue on reset: 0"]
113#[derive(Clone, Copy, Debug, PartialEq)]
114pub enum DIV_MODE_A {
115    #[doc = "0: Use PDM_LEFT in sampler"]
116    LEFT = 0,
117    #[doc = "1: Use PDM_RIGHT in sampler"]
118    RIGHT = 1,
119}
120impl From<DIV_MODE_A> for bool {
121    #[inline(always)]
122    fn from(variant: DIV_MODE_A) -> Self {
123        variant as u8 != 0
124    }
125}
126#[doc = "Field `DIV_MODE` reader - Select which divider to use in sampler"]
127pub struct DIV_MODE_R(crate::FieldReader<bool, DIV_MODE_A>);
128impl DIV_MODE_R {
129    #[inline(always)]
130    pub(crate) fn new(bits: bool) -> Self {
131        DIV_MODE_R(crate::FieldReader::new(bits))
132    }
133    #[doc = r"Get enumerated values variant"]
134    #[inline(always)]
135    pub fn variant(&self) -> DIV_MODE_A {
136        match self.bits {
137            false => DIV_MODE_A::LEFT,
138            true => DIV_MODE_A::RIGHT,
139        }
140    }
141    #[doc = "Checks if the value of the field is `LEFT`"]
142    #[inline(always)]
143    pub fn is_left(&self) -> bool {
144        **self == DIV_MODE_A::LEFT
145    }
146    #[doc = "Checks if the value of the field is `RIGHT`"]
147    #[inline(always)]
148    pub fn is_right(&self) -> bool {
149        **self == DIV_MODE_A::RIGHT
150    }
151}
152impl core::ops::Deref for DIV_MODE_R {
153    type Target = crate::FieldReader<bool, DIV_MODE_A>;
154    #[inline(always)]
155    fn deref(&self) -> &Self::Target {
156        &self.0
157    }
158}
159#[doc = "Field `DIV_MODE` writer - Select which divider to use in sampler"]
160pub struct DIV_MODE_W<'a> {
161    w: &'a mut W,
162}
163impl<'a> DIV_MODE_W<'a> {
164    #[doc = r"Writes `variant` to the field"]
165    #[inline(always)]
166    pub fn variant(self, variant: DIV_MODE_A) -> &'a mut W {
167        self.bit(variant.into())
168    }
169    #[doc = "Use PDM_LEFT in sampler"]
170    #[inline(always)]
171    pub fn left(self) -> &'a mut W {
172        self.variant(DIV_MODE_A::LEFT)
173    }
174    #[doc = "Use PDM_RIGHT in sampler"]
175    #[inline(always)]
176    pub fn right(self) -> &'a mut W {
177        self.variant(DIV_MODE_A::RIGHT)
178    }
179    #[doc = r"Sets the field bit"]
180    #[inline(always)]
181    pub fn set_bit(self) -> &'a mut W {
182        self.bit(true)
183    }
184    #[doc = r"Clears the field bit"]
185    #[inline(always)]
186    pub fn clear_bit(self) -> &'a mut W {
187        self.bit(false)
188    }
189    #[doc = r"Writes raw bits to the field"]
190    #[inline(always)]
191    pub fn bit(self, value: bool) -> &'a mut W {
192        self.w.bits =
193            (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
194        self.w
195    }
196}
197#[doc = "Field `S_CYCLES` reader - Set number of PDM_CLK during gain setting changes or soft mute"]
198pub struct S_CYCLES_R(crate::FieldReader<u8, u8>);
199impl S_CYCLES_R {
200    #[inline(always)]
201    pub(crate) fn new(bits: u8) -> Self {
202        S_CYCLES_R(crate::FieldReader::new(bits))
203    }
204}
205impl core::ops::Deref for S_CYCLES_R {
206    type Target = crate::FieldReader<u8, u8>;
207    #[inline(always)]
208    fn deref(&self) -> &Self::Target {
209        &self.0
210    }
211}
212#[doc = "Field `S_CYCLES` writer - Set number of PDM_CLK during gain setting changes or soft mute"]
213pub struct S_CYCLES_W<'a> {
214    w: &'a mut W,
215}
216impl<'a> S_CYCLES_W<'a> {
217    #[doc = r"Writes raw bits to the field"]
218    #[inline(always)]
219    pub unsafe fn bits(self, value: u8) -> &'a mut W {
220        self.w.bits =
221            (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3);
222        self.w
223    }
224}
225#[doc = "Field `HP_GAIN` reader - Adjust high pass filter coefficients"]
226pub struct HP_GAIN_R(crate::FieldReader<u8, u8>);
227impl HP_GAIN_R {
228    #[inline(always)]
229    pub(crate) fn new(bits: u8) -> Self {
230        HP_GAIN_R(crate::FieldReader::new(bits))
231    }
232}
233impl core::ops::Deref for HP_GAIN_R {
234    type Target = crate::FieldReader<u8, u8>;
235    #[inline(always)]
236    fn deref(&self) -> &Self::Target {
237        &self.0
238    }
239}
240#[doc = "Field `HP_GAIN` writer - Adjust high pass filter coefficients"]
241pub struct HP_GAIN_W<'a> {
242    w: &'a mut W,
243}
244impl<'a> HP_GAIN_W<'a> {
245    #[doc = r"Writes raw bits to the field"]
246    #[inline(always)]
247    pub unsafe fn bits(self, value: u8) -> &'a mut W {
248        self.w.bits =
249            (self.w.bits & !(0x0f << 6)) | ((value as u32 & 0x0f) << 6);
250        self.w
251    }
252}
253#[doc = "Field `ADCHPD` reader - Set to disable high pass filter"]
254pub struct ADCHPD_R(crate::FieldReader<bool, bool>);
255impl ADCHPD_R {
256    #[inline(always)]
257    pub(crate) fn new(bits: bool) -> Self {
258        ADCHPD_R(crate::FieldReader::new(bits))
259    }
260}
261impl core::ops::Deref for ADCHPD_R {
262    type Target = crate::FieldReader<bool, bool>;
263    #[inline(always)]
264    fn deref(&self) -> &Self::Target {
265        &self.0
266    }
267}
268#[doc = "Field `ADCHPD` writer - Set to disable high pass filter"]
269pub struct ADCHPD_W<'a> {
270    w: &'a mut W,
271}
272impl<'a> ADCHPD_W<'a> {
273    #[doc = r"Sets the field bit"]
274    #[inline(always)]
275    pub fn set_bit(self) -> &'a mut W {
276        self.bit(true)
277    }
278    #[doc = r"Clears the field bit"]
279    #[inline(always)]
280    pub fn clear_bit(self) -> &'a mut W {
281        self.bit(false)
282    }
283    #[doc = r"Writes raw bits to the field"]
284    #[inline(always)]
285    pub fn bit(self, value: bool) -> &'a mut W {
286        self.w.bits =
287            (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
288        self.w
289    }
290}
291#[doc = "Field `M_CLK_DIV` reader - PDM_CLK frquency divisor"]
292pub struct M_CLK_DIV_R(crate::FieldReader<u8, u8>);
293impl M_CLK_DIV_R {
294    #[inline(always)]
295    pub(crate) fn new(bits: u8) -> Self {
296        M_CLK_DIV_R(crate::FieldReader::new(bits))
297    }
298}
299impl core::ops::Deref for M_CLK_DIV_R {
300    type Target = crate::FieldReader<u8, u8>;
301    #[inline(always)]
302    fn deref(&self) -> &Self::Target {
303        &self.0
304    }
305}
306#[doc = "Field `M_CLK_DIV` writer - PDM_CLK frquency divisor"]
307pub struct M_CLK_DIV_W<'a> {
308    w: &'a mut W,
309}
310impl<'a> M_CLK_DIV_W<'a> {
311    #[doc = r"Writes raw bits to the field"]
312    #[inline(always)]
313    pub unsafe fn bits(self, value: u8) -> &'a mut W {
314        self.w.bits =
315            (self.w.bits & !(0x03 << 11)) | ((value as u32 & 0x03) << 11);
316        self.w
317    }
318}
319#[doc = "Field `SINC_RATE` reader - SINC decimation rate"]
320pub struct SINC_RATE_R(crate::FieldReader<u8, u8>);
321impl SINC_RATE_R {
322    #[inline(always)]
323    pub(crate) fn new(bits: u8) -> Self {
324        SINC_RATE_R(crate::FieldReader::new(bits))
325    }
326}
327impl core::ops::Deref for SINC_RATE_R {
328    type Target = crate::FieldReader<u8, u8>;
329    #[inline(always)]
330    fn deref(&self) -> &Self::Target {
331        &self.0
332    }
333}
334#[doc = "Field `SINC_RATE` writer - SINC decimation rate"]
335pub struct SINC_RATE_W<'a> {
336    w: &'a mut W,
337}
338impl<'a> SINC_RATE_W<'a> {
339    #[doc = r"Writes raw bits to the field"]
340    #[inline(always)]
341    pub unsafe fn bits(self, value: u8) -> &'a mut W {
342        self.w.bits =
343            (self.w.bits & !(0x7f << 13)) | ((value as u32 & 0x7f) << 13);
344        self.w
345    }
346}
347#[doc = "Field `PGA_L` reader - Left channel PGA gain"]
348pub struct PGA_L_R(crate::FieldReader<u8, u8>);
349impl PGA_L_R {
350    #[inline(always)]
351    pub(crate) fn new(bits: u8) -> Self {
352        PGA_L_R(crate::FieldReader::new(bits))
353    }
354}
355impl core::ops::Deref for PGA_L_R {
356    type Target = crate::FieldReader<u8, u8>;
357    #[inline(always)]
358    fn deref(&self) -> &Self::Target {
359        &self.0
360    }
361}
362#[doc = "Field `PGA_L` writer - Left channel PGA gain"]
363pub struct PGA_L_W<'a> {
364    w: &'a mut W,
365}
366impl<'a> PGA_L_W<'a> {
367    #[doc = r"Writes raw bits to the field"]
368    #[inline(always)]
369    pub unsafe fn bits(self, value: u8) -> &'a mut W {
370        self.w.bits =
371            (self.w.bits & !(0x1f << 20)) | ((value as u32 & 0x1f) << 20);
372        self.w
373    }
374}
375#[doc = "Field `PGA_R` reader - Right channel PGA gain"]
376pub struct PGA_R_R(crate::FieldReader<u8, u8>);
377impl PGA_R_R {
378    #[inline(always)]
379    pub(crate) fn new(bits: u8) -> Self {
380        PGA_R_R(crate::FieldReader::new(bits))
381    }
382}
383impl core::ops::Deref for PGA_R_R {
384    type Target = crate::FieldReader<u8, u8>;
385    #[inline(always)]
386    fn deref(&self) -> &Self::Target {
387        &self.0
388    }
389}
390#[doc = "Field `PGA_R` writer - Right channel PGA gain"]
391pub struct PGA_R_W<'a> {
392    w: &'a mut W,
393}
394impl<'a> PGA_R_W<'a> {
395    #[doc = r"Writes raw bits to the field"]
396    #[inline(always)]
397    pub unsafe fn bits(self, value: u8) -> &'a mut W {
398        self.w.bits =
399            (self.w.bits & !(0x1f << 25)) | ((value as u32 & 0x1f) << 25);
400        self.w
401    }
402}
403#[doc = "Field `DMICK_DLY` reader - Input data sampling with PDM clock cycle delay"]
404pub struct DMICK_DLY_R(crate::FieldReader<bool, bool>);
405impl DMICK_DLY_R {
406    #[inline(always)]
407    pub(crate) fn new(bits: bool) -> Self {
408        DMICK_DLY_R(crate::FieldReader::new(bits))
409    }
410}
411impl core::ops::Deref for DMICK_DLY_R {
412    type Target = crate::FieldReader<bool, bool>;
413    #[inline(always)]
414    fn deref(&self) -> &Self::Target {
415        &self.0
416    }
417}
418#[doc = "Field `DMICK_DLY` writer - Input data sampling with PDM clock cycle delay"]
419pub struct DMICK_DLY_W<'a> {
420    w: &'a mut W,
421}
422impl<'a> DMICK_DLY_W<'a> {
423    #[doc = r"Sets the field bit"]
424    #[inline(always)]
425    pub fn set_bit(self) -> &'a mut W {
426        self.bit(true)
427    }
428    #[doc = r"Clears the field bit"]
429    #[inline(always)]
430    pub fn clear_bit(self) -> &'a mut W {
431        self.bit(false)
432    }
433    #[doc = r"Writes raw bits to the field"]
434    #[inline(always)]
435    pub fn bit(self, value: bool) -> &'a mut W {
436        self.w.bits =
437            (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
438        self.w
439    }
440}
441#[doc = "Field `DIV_WD_MODE` reader - Status IN detection windows"]
442pub struct DIV_WD_MODE_R(crate::FieldReader<bool, bool>);
443impl DIV_WD_MODE_R {
444    #[inline(always)]
445    pub(crate) fn new(bits: bool) -> Self {
446        DIV_WD_MODE_R(crate::FieldReader::new(bits))
447    }
448}
449impl core::ops::Deref for DIV_WD_MODE_R {
450    type Target = crate::FieldReader<bool, bool>;
451    #[inline(always)]
452    fn deref(&self) -> &Self::Target {
453        &self.0
454    }
455}
456#[doc = "Field `DIV_WD_MODE` writer - Status IN detection windows"]
457pub struct DIV_WD_MODE_W<'a> {
458    w: &'a mut W,
459}
460impl<'a> DIV_WD_MODE_W<'a> {
461    #[doc = r"Sets the field bit"]
462    #[inline(always)]
463    pub fn set_bit(self) -> &'a mut W {
464        self.bit(true)
465    }
466    #[doc = r"Clears the field bit"]
467    #[inline(always)]
468    pub fn clear_bit(self) -> &'a mut W {
469        self.bit(false)
470    }
471    #[doc = r"Writes raw bits to the field"]
472    #[inline(always)]
473    pub fn bit(self, value: bool) -> &'a mut W {
474        self.w.bits =
475            (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
476        self.w
477    }
478}
479impl R {
480    #[doc = "Bit 0 - Set to enable PDM core"]
481    #[inline(always)]
482    pub fn pdm_core_config(&self) -> PDM_CORE_CONFIG_R {
483        PDM_CORE_CONFIG_R::new((self.bits & 0x01) != 0)
484    }
485    #[doc = "Bit 1 - Set to enable PDM Soft mute"]
486    #[inline(always)]
487    pub fn soft_mute(&self) -> SOFT_MUTE_R {
488        SOFT_MUTE_R::new(((self.bits >> 1) & 0x01) != 0)
489    }
490    #[doc = "Bit 2 - Select which divider to use in sampler"]
491    #[inline(always)]
492    pub fn div_mode(&self) -> DIV_MODE_R {
493        DIV_MODE_R::new(((self.bits >> 2) & 0x01) != 0)
494    }
495    #[doc = "Bits 3:5 - Set number of PDM_CLK during gain setting changes or soft mute"]
496    #[inline(always)]
497    pub fn s_cycles(&self) -> S_CYCLES_R {
498        S_CYCLES_R::new(((self.bits >> 3) & 0x07) as u8)
499    }
500    #[doc = "Bits 6:9 - Adjust high pass filter coefficients"]
501    #[inline(always)]
502    pub fn hp_gain(&self) -> HP_GAIN_R {
503        HP_GAIN_R::new(((self.bits >> 6) & 0x0f) as u8)
504    }
505    #[doc = "Bit 10 - Set to disable high pass filter"]
506    #[inline(always)]
507    pub fn adchpd(&self) -> ADCHPD_R {
508        ADCHPD_R::new(((self.bits >> 10) & 0x01) != 0)
509    }
510    #[doc = "Bits 11:12 - PDM_CLK frquency divisor"]
511    #[inline(always)]
512    pub fn m_clk_div(&self) -> M_CLK_DIV_R {
513        M_CLK_DIV_R::new(((self.bits >> 11) & 0x03) as u8)
514    }
515    #[doc = "Bits 13:19 - SINC decimation rate"]
516    #[inline(always)]
517    pub fn sinc_rate(&self) -> SINC_RATE_R {
518        SINC_RATE_R::new(((self.bits >> 13) & 0x7f) as u8)
519    }
520    #[doc = "Bits 20:24 - Left channel PGA gain"]
521    #[inline(always)]
522    pub fn pga_l(&self) -> PGA_L_R {
523        PGA_L_R::new(((self.bits >> 20) & 0x1f) as u8)
524    }
525    #[doc = "Bits 25:29 - Right channel PGA gain"]
526    #[inline(always)]
527    pub fn pga_r(&self) -> PGA_R_R {
528        PGA_R_R::new(((self.bits >> 25) & 0x1f) as u8)
529    }
530    #[doc = "Bit 30 - Input data sampling with PDM clock cycle delay"]
531    #[inline(always)]
532    pub fn dmick_dly(&self) -> DMICK_DLY_R {
533        DMICK_DLY_R::new(((self.bits >> 30) & 0x01) != 0)
534    }
535    #[doc = "Bit 31 - Status IN detection windows"]
536    #[inline(always)]
537    pub fn div_wd_mode(&self) -> DIV_WD_MODE_R {
538        DIV_WD_MODE_R::new(((self.bits >> 31) & 0x01) != 0)
539    }
540}
541impl W {
542    #[doc = "Bit 0 - Set to enable PDM core"]
543    #[inline(always)]
544    pub fn pdm_core_config(&mut self) -> PDM_CORE_CONFIG_W {
545        PDM_CORE_CONFIG_W { w: self }
546    }
547    #[doc = "Bit 1 - Set to enable PDM Soft mute"]
548    #[inline(always)]
549    pub fn soft_mute(&mut self) -> SOFT_MUTE_W {
550        SOFT_MUTE_W { w: self }
551    }
552    #[doc = "Bit 2 - Select which divider to use in sampler"]
553    #[inline(always)]
554    pub fn div_mode(&mut self) -> DIV_MODE_W {
555        DIV_MODE_W { w: self }
556    }
557    #[doc = "Bits 3:5 - Set number of PDM_CLK during gain setting changes or soft mute"]
558    #[inline(always)]
559    pub fn s_cycles(&mut self) -> S_CYCLES_W {
560        S_CYCLES_W { w: self }
561    }
562    #[doc = "Bits 6:9 - Adjust high pass filter coefficients"]
563    #[inline(always)]
564    pub fn hp_gain(&mut self) -> HP_GAIN_W {
565        HP_GAIN_W { w: self }
566    }
567    #[doc = "Bit 10 - Set to disable high pass filter"]
568    #[inline(always)]
569    pub fn adchpd(&mut self) -> ADCHPD_W {
570        ADCHPD_W { w: self }
571    }
572    #[doc = "Bits 11:12 - PDM_CLK frquency divisor"]
573    #[inline(always)]
574    pub fn m_clk_div(&mut self) -> M_CLK_DIV_W {
575        M_CLK_DIV_W { w: self }
576    }
577    #[doc = "Bits 13:19 - SINC decimation rate"]
578    #[inline(always)]
579    pub fn sinc_rate(&mut self) -> SINC_RATE_W {
580        SINC_RATE_W { w: self }
581    }
582    #[doc = "Bits 20:24 - Left channel PGA gain"]
583    #[inline(always)]
584    pub fn pga_l(&mut self) -> PGA_L_W {
585        PGA_L_W { w: self }
586    }
587    #[doc = "Bits 25:29 - Right channel PGA gain"]
588    #[inline(always)]
589    pub fn pga_r(&mut self) -> PGA_R_W {
590        PGA_R_W { w: self }
591    }
592    #[doc = "Bit 30 - Input data sampling with PDM clock cycle delay"]
593    #[inline(always)]
594    pub fn dmick_dly(&mut self) -> DMICK_DLY_W {
595        DMICK_DLY_W { w: self }
596    }
597    #[doc = "Bit 31 - Status IN detection windows"]
598    #[inline(always)]
599    pub fn div_wd_mode(&mut self) -> DIV_WD_MODE_W {
600        DIV_WD_MODE_W { w: self }
601    }
602    #[doc = "Writes raw bits to the register."]
603    #[inline(always)]
604    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
605        self.0.bits(bits);
606        self
607    }
608}
609#[doc = "PDM2PCM core configure register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdm_core_config](index.html) module"]
610pub struct PDM_CORE_CONFIG_SPEC;
611impl crate::RegisterSpec for PDM_CORE_CONFIG_SPEC {
612    type Ux = u32;
613}
614#[doc = "`read()` method returns [pdm_core_config::R](R) reader structure"]
615impl crate::Readable for PDM_CORE_CONFIG_SPEC {
616    type Reader = R;
617}
618#[doc = "`write(|w| ..)` method takes [pdm_core_config::W](W) writer structure"]
619impl crate::Writable for PDM_CORE_CONFIG_SPEC {
620    type Writer = W;
621}
622#[doc = "`reset()` method sets PDM_CORE_CONFIG to value 0x1082_66c9"]
623impl crate::Resettable for PDM_CORE_CONFIG_SPEC {
624    #[inline(always)]
625    fn reset_value() -> Self::Ux {
626        0x1082_66c9
627    }
628}
eos_s3/aud/pdm_core_config.rs

eos_s3/aud/
pdm_core_config.rs
