embassy_stm32/eth/v2/
mod.rs

1mod descriptors;
2
3use core::marker::PhantomData;
4use core::sync::atomic::{fence, Ordering};
5
6use embassy_hal_internal::{into_ref, PeripheralRef};
7use stm32_metapac::syscfg::vals::EthSelPhy;
8
9pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
10use super::*;
11use crate::gpio::{AfType, AnyPin, OutputType, SealedPin as _, Speed};
12use crate::interrupt::InterruptExt;
13use crate::pac::ETH;
14use crate::rcc::SealedRccPeripheral;
15use crate::{interrupt, Peripheral};
16
17/// Interrupt handler.
18pub struct InterruptHandler {}
19
20impl interrupt::typelevel::Handler<interrupt::typelevel::ETH> for InterruptHandler {
21    unsafe fn on_interrupt() {
22        WAKER.wake();
23
24        // TODO: Check and clear more flags
25        let dma = ETH.ethernet_dma();
26
27        dma.dmacsr().modify(|w| {
28            w.set_ti(true);
29            w.set_ri(true);
30            w.set_nis(true);
31        });
32        // Delay two peripheral's clock
33        dma.dmacsr().read();
34        dma.dmacsr().read();
35    }
36}
37
38/// Ethernet driver.
39pub struct Ethernet<'d, T: Instance, P: PHY> {
40    _peri: PeripheralRef<'d, T>,
41    pub(crate) tx: TDesRing<'d>,
42    pub(crate) rx: RDesRing<'d>,
43    pins: Pins<'d>,
44    pub(crate) phy: P,
45    pub(crate) station_management: EthernetStationManagement<T>,
46    pub(crate) mac_addr: [u8; 6],
47}
48
49/// Pins of ethernet driver.
50enum Pins<'d> {
51    Rmii([PeripheralRef<'d, AnyPin>; 9]),
52    Mii([PeripheralRef<'d, AnyPin>; 14]),
53}
54
55macro_rules! config_pins {
56    ($($pin:ident),*) => {
57        critical_section::with(|_| {
58            $(
59                // TODO: shouldn't some pins be configured as inputs?
60                $pin.set_as_af($pin.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
61            )*
62        })
63    };
64}
65
66impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
67    /// Create a new RMII ethernet driver using 9 pins.
68    pub fn new<const TX: usize, const RX: usize>(
69        queue: &'d mut PacketQueue<TX, RX>,
70        peri: impl Peripheral<P = T> + 'd,
71        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
72        ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
73        mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
74        mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
75        crs: impl Peripheral<P = impl CRSPin<T>> + 'd,
76        rx_d0: impl Peripheral<P = impl RXD0Pin<T>> + 'd,
77        rx_d1: impl Peripheral<P = impl RXD1Pin<T>> + 'd,
78        tx_d0: impl Peripheral<P = impl TXD0Pin<T>> + 'd,
79        tx_d1: impl Peripheral<P = impl TXD1Pin<T>> + 'd,
80        tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
81        phy: P,
82        mac_addr: [u8; 6],
83    ) -> Self {
84        // Enable the necessary clocks
85        critical_section::with(|_| {
86            crate::pac::RCC.ahb1enr().modify(|w| {
87                w.set_ethen(true);
88                w.set_ethtxen(true);
89                w.set_ethrxen(true);
90            });
91
92            crate::pac::SYSCFG.pmcr().modify(|w| w.set_eth_sel_phy(EthSelPhy::RMII));
93        });
94
95        into_ref!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
96        config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
97
98        let pins = Pins::Rmii([
99            ref_clk.map_into(),
100            mdio.map_into(),
101            mdc.map_into(),
102            crs.map_into(),
103            rx_d0.map_into(),
104            rx_d1.map_into(),
105            tx_d0.map_into(),
106            tx_d1.map_into(),
107            tx_en.map_into(),
108        ]);
109
110        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
111    }
112
113    /// Create a new MII ethernet driver using 14 pins.
114    pub fn new_mii<const TX: usize, const RX: usize>(
115        queue: &'d mut PacketQueue<TX, RX>,
116        peri: impl Peripheral<P = T> + 'd,
117        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
118        rx_clk: impl Peripheral<P = impl RXClkPin<T>> + 'd,
119        tx_clk: impl Peripheral<P = impl TXClkPin<T>> + 'd,
120        mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
121        mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
122        rxdv: impl Peripheral<P = impl RXDVPin<T>> + 'd,
123        rx_d0: impl Peripheral<P = impl RXD0Pin<T>> + 'd,
124        rx_d1: impl Peripheral<P = impl RXD1Pin<T>> + 'd,
125        rx_d2: impl Peripheral<P = impl RXD2Pin<T>> + 'd,
126        rx_d3: impl Peripheral<P = impl RXD3Pin<T>> + 'd,
127        tx_d0: impl Peripheral<P = impl TXD0Pin<T>> + 'd,
128        tx_d1: impl Peripheral<P = impl TXD1Pin<T>> + 'd,
129        tx_d2: impl Peripheral<P = impl TXD2Pin<T>> + 'd,
130        tx_d3: impl Peripheral<P = impl TXD3Pin<T>> + 'd,
131        tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
132        phy: P,
133        mac_addr: [u8; 6],
134    ) -> Self {
135        // Enable the necessary clocks
136        critical_section::with(|_| {
137            crate::pac::RCC.ahb1enr().modify(|w| {
138                w.set_ethen(true);
139                w.set_ethtxen(true);
140                w.set_ethrxen(true);
141            });
142
143            crate::pac::SYSCFG
144                .pmcr()
145                .modify(|w| w.set_eth_sel_phy(EthSelPhy::MII_GMII));
146        });
147
148        into_ref!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
149        config_pins!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
150
151        let pins = Pins::Mii([
152            rx_clk.map_into(),
153            tx_clk.map_into(),
154            mdio.map_into(),
155            mdc.map_into(),
156            rxdv.map_into(),
157            rx_d0.map_into(),
158            rx_d1.map_into(),
159            rx_d2.map_into(),
160            rx_d3.map_into(),
161            tx_d0.map_into(),
162            tx_d1.map_into(),
163            tx_d2.map_into(),
164            tx_d3.map_into(),
165            tx_en.map_into(),
166        ]);
167
168        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
169    }
170
171    fn new_inner<const TX: usize, const RX: usize>(
172        queue: &'d mut PacketQueue<TX, RX>,
173        peri: impl Peripheral<P = T> + 'd,
174        _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
175        pins: Pins<'d>,
176        phy: P,
177        mac_addr: [u8; 6],
178    ) -> Self {
179        let dma = T::regs().ethernet_dma();
180        let mac = T::regs().ethernet_mac();
181        let mtl = T::regs().ethernet_mtl();
182
183        // Reset and wait
184        dma.dmamr().modify(|w| w.set_swr(true));
185        while dma.dmamr().read().swr() {}
186
187        mac.maccr().modify(|w| {
188            w.set_ipg(0b000); // 96 bit times
189            w.set_acs(true);
190            w.set_fes(true);
191            w.set_dm(true);
192            // TODO: Carrier sense ? ECRSFD
193        });
194
195        // Disable multicast filter
196        mac.macpfr().modify(|w| w.set_pm(true));
197
198        // Note: Writing to LR triggers synchronisation of both LR and HR into the MAC core,
199        // so the LR write must happen after the HR write.
200        mac.maca0hr()
201            .modify(|w| w.set_addrhi(u16::from(mac_addr[4]) | (u16::from(mac_addr[5]) << 8)));
202        mac.maca0lr().write(|w| {
203            w.set_addrlo(
204                u32::from(mac_addr[0])
205                    | (u32::from(mac_addr[1]) << 8)
206                    | (u32::from(mac_addr[2]) << 16)
207                    | (u32::from(mac_addr[3]) << 24),
208            )
209        });
210
211        mac.macqtx_fcr().modify(|w| w.set_pt(0x100));
212
213        // disable all MMC RX interrupts
214        mac.mmc_rx_interrupt_mask().write(|w| {
215            w.set_rxcrcerpim(true);
216            w.set_rxalgnerpim(true);
217            w.set_rxucgpim(true);
218            w.set_rxlpiuscim(true);
219            w.set_rxlpitrcim(true)
220        });
221
222        // disable all MMC TX interrupts
223        mac.mmc_tx_interrupt_mask().write(|w| {
224            w.set_txscolgpim(true);
225            w.set_txmcolgpim(true);
226            w.set_txgpktim(true);
227            w.set_txlpiuscim(true);
228            w.set_txlpitrcim(true);
229        });
230
231        mtl.mtlrx_qomr().modify(|w| w.set_rsf(true));
232        mtl.mtltx_qomr().modify(|w| w.set_tsf(true));
233
234        dma.dmactx_cr().modify(|w| w.set_txpbl(1)); // 32 ?
235        dma.dmacrx_cr().modify(|w| {
236            w.set_rxpbl(1); // 32 ?
237            w.set_rbsz(RX_BUFFER_SIZE as u16);
238        });
239
240        let hclk = <T as SealedRccPeripheral>::frequency();
241        let hclk_mhz = hclk.0 / 1_000_000;
242
243        // Set the MDC clock frequency in the range 1MHz - 2.5MHz
244        let clock_range = match hclk_mhz {
245            0..=34 => 2,    // Divide by 16
246            35..=59 => 3,   // Divide by 26
247            60..=99 => 0,   // Divide by 42
248            100..=149 => 1, // Divide by 62
249            150..=249 => 4, // Divide by 102
250            250..=310 => 5, // Divide by 124
251            _ => {
252                panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
253            }
254        };
255
256        let mut this = Self {
257            _peri: peri.into_ref(),
258            tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
259            rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
260            pins,
261            phy,
262            station_management: EthernetStationManagement {
263                peri: PhantomData,
264                clock_range: clock_range,
265            },
266            mac_addr,
267        };
268
269        fence(Ordering::SeqCst);
270
271        let mac = T::regs().ethernet_mac();
272        let mtl = T::regs().ethernet_mtl();
273        let dma = T::regs().ethernet_dma();
274
275        mac.maccr().modify(|w| {
276            w.set_re(true);
277            w.set_te(true);
278        });
279        mtl.mtltx_qomr().modify(|w| w.set_ftq(true));
280
281        dma.dmactx_cr().modify(|w| w.set_st(true));
282        dma.dmacrx_cr().modify(|w| w.set_sr(true));
283
284        // Enable interrupts
285        dma.dmacier().modify(|w| {
286            w.set_nie(true);
287            w.set_rie(true);
288            w.set_tie(true);
289        });
290
291        this.phy.phy_reset(&mut this.station_management);
292        this.phy.phy_init(&mut this.station_management);
293
294        interrupt::ETH.unpend();
295        unsafe { interrupt::ETH.enable() };
296
297        this
298    }
299}
300
301/// Ethernet SMI driver.
302pub struct EthernetStationManagement<T: Instance> {
303    peri: PhantomData<T>,
304    clock_range: u8,
305}
306
307unsafe impl<T: Instance> StationManagement for EthernetStationManagement<T> {
308    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
309        let mac = T::regs().ethernet_mac();
310
311        mac.macmdioar().modify(|w| {
312            w.set_pa(phy_addr);
313            w.set_rda(reg);
314            w.set_goc(0b11); // read
315            w.set_cr(self.clock_range);
316            w.set_mb(true);
317        });
318        while mac.macmdioar().read().mb() {}
319        mac.macmdiodr().read().md()
320    }
321
322    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
323        let mac = T::regs().ethernet_mac();
324
325        mac.macmdiodr().write(|w| w.set_md(val));
326        mac.macmdioar().modify(|w| {
327            w.set_pa(phy_addr);
328            w.set_rda(reg);
329            w.set_goc(0b01); // write
330            w.set_cr(self.clock_range);
331            w.set_mb(true);
332        });
333        while mac.macmdioar().read().mb() {}
334    }
335}
336
337impl<'d, T: Instance, P: PHY> Drop for Ethernet<'d, T, P> {
338    fn drop(&mut self) {
339        let dma = T::regs().ethernet_dma();
340        let mac = T::regs().ethernet_mac();
341        let mtl = T::regs().ethernet_mtl();
342
343        // Disable the TX DMA and wait for any previous transmissions to be completed
344        dma.dmactx_cr().modify(|w| w.set_st(false));
345        while {
346            let txqueue = mtl.mtltx_qdr().read();
347            txqueue.trcsts() == 0b01 || txqueue.txqsts()
348        } {}
349
350        // Disable MAC transmitter and receiver
351        mac.maccr().modify(|w| {
352            w.set_re(false);
353            w.set_te(false);
354        });
355
356        // Wait for previous receiver transfers to be completed and then disable the RX DMA
357        while {
358            let rxqueue = mtl.mtlrx_qdr().read();
359            rxqueue.rxqsts() != 0b00 || rxqueue.prxq() != 0
360        } {}
361        dma.dmacrx_cr().modify(|w| w.set_sr(false));
362
363        critical_section::with(|_| {
364            for pin in match self.pins {
365                Pins::Rmii(ref mut pins) => pins.iter_mut(),
366                Pins::Mii(ref mut pins) => pins.iter_mut(),
367            } {
368                pin.set_as_disconnected();
369            }
370        })
371    }
372}
embassy_stm32/eth/v2/mod.rs

embassy_stm32/eth/v2/
mod.rs
