embassy_stm32/eth/v2/
mod.rs

1mod descriptors;
2
3use core::marker::PhantomData;
4use core::sync::atomic::{fence, Ordering};
5
6use embassy_hal_internal::Peri;
7use stm32_metapac::syscfg::vals::EthSelPhy;
8
9pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
10use super::*;
11use crate::gpio::{AfType, AnyPin, OutputType, SealedPin as _, Speed};
12use crate::interrupt;
13use crate::interrupt::InterruptExt;
14use crate::pac::ETH;
15use crate::rcc::SealedRccPeripheral;
16
17/// Interrupt handler.
18pub struct InterruptHandler {}
19
20impl interrupt::typelevel::Handler<interrupt::typelevel::ETH> for InterruptHandler {
21    unsafe fn on_interrupt() {
22        WAKER.wake();
23
24        // TODO: Check and clear more flags
25        let dma = ETH.ethernet_dma();
26
27        dma.dmacsr().modify(|w| {
28            w.set_ti(true);
29            w.set_ri(true);
30            w.set_nis(true);
31        });
32        // Delay two peripheral's clock
33        dma.dmacsr().read();
34        dma.dmacsr().read();
35    }
36}
37
38/// Ethernet driver.
39pub struct Ethernet<'d, T: Instance, P: Phy> {
40    _peri: Peri<'d, T>,
41    pub(crate) tx: TDesRing<'d>,
42    pub(crate) rx: RDesRing<'d>,
43    pins: Pins<'d>,
44    pub(crate) phy: P,
45    pub(crate) station_management: EthernetStationManagement<T>,
46    pub(crate) mac_addr: [u8; 6],
47}
48
49/// Pins of ethernet driver.
50enum Pins<'d> {
51    Rmii([Peri<'d, AnyPin>; 9]),
52    Mii([Peri<'d, AnyPin>; 14]),
53}
54
55macro_rules! config_pins {
56    ($($pin:ident),*) => {
57        critical_section::with(|_| {
58            $(
59                // TODO: shouldn't some pins be configured as inputs?
60                $pin.set_as_af($pin.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
61            )*
62        })
63    };
64}
65
66impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
67    /// Create a new RMII ethernet driver using 9 pins.
68    pub fn new<const TX: usize, const RX: usize>(
69        queue: &'d mut PacketQueue<TX, RX>,
70        peri: Peri<'d, T>,
71        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
72        ref_clk: Peri<'d, impl RefClkPin<T>>,
73        mdio: Peri<'d, impl MDIOPin<T>>,
74        mdc: Peri<'d, impl MDCPin<T>>,
75        crs: Peri<'d, impl CRSPin<T>>,
76        rx_d0: Peri<'d, impl RXD0Pin<T>>,
77        rx_d1: Peri<'d, impl RXD1Pin<T>>,
78        tx_d0: Peri<'d, impl TXD0Pin<T>>,
79        tx_d1: Peri<'d, impl TXD1Pin<T>>,
80        tx_en: Peri<'d, impl TXEnPin<T>>,
81        phy: P,
82        mac_addr: [u8; 6],
83    ) -> Self {
84        // Enable the necessary clocks
85        critical_section::with(|_| {
86            crate::pac::RCC.ahb1enr().modify(|w| {
87                w.set_ethen(true);
88                w.set_ethtxen(true);
89                w.set_ethrxen(true);
90            });
91
92            crate::pac::SYSCFG.pmcr().modify(|w| w.set_eth_sel_phy(EthSelPhy::RMII));
93        });
94
95        config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
96
97        let pins = Pins::Rmii([
98            ref_clk.into(),
99            mdio.into(),
100            mdc.into(),
101            crs.into(),
102            rx_d0.into(),
103            rx_d1.into(),
104            tx_d0.into(),
105            tx_d1.into(),
106            tx_en.into(),
107        ]);
108
109        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
110    }
111
112    /// Create a new MII ethernet driver using 14 pins.
113    pub fn new_mii<const TX: usize, const RX: usize>(
114        queue: &'d mut PacketQueue<TX, RX>,
115        peri: Peri<'d, T>,
116        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
117        rx_clk: Peri<'d, impl RXClkPin<T>>,
118        tx_clk: Peri<'d, impl TXClkPin<T>>,
119        mdio: Peri<'d, impl MDIOPin<T>>,
120        mdc: Peri<'d, impl MDCPin<T>>,
121        rxdv: Peri<'d, impl RXDVPin<T>>,
122        rx_d0: Peri<'d, impl RXD0Pin<T>>,
123        rx_d1: Peri<'d, impl RXD1Pin<T>>,
124        rx_d2: Peri<'d, impl RXD2Pin<T>>,
125        rx_d3: Peri<'d, impl RXD3Pin<T>>,
126        tx_d0: Peri<'d, impl TXD0Pin<T>>,
127        tx_d1: Peri<'d, impl TXD1Pin<T>>,
128        tx_d2: Peri<'d, impl TXD2Pin<T>>,
129        tx_d3: Peri<'d, impl TXD3Pin<T>>,
130        tx_en: Peri<'d, impl TXEnPin<T>>,
131        phy: P,
132        mac_addr: [u8; 6],
133    ) -> Self {
134        // Enable the necessary clocks
135        critical_section::with(|_| {
136            crate::pac::RCC.ahb1enr().modify(|w| {
137                w.set_ethen(true);
138                w.set_ethtxen(true);
139                w.set_ethrxen(true);
140            });
141
142            crate::pac::SYSCFG
143                .pmcr()
144                .modify(|w| w.set_eth_sel_phy(EthSelPhy::MII_GMII));
145        });
146
147        config_pins!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
148
149        let pins = Pins::Mii([
150            rx_clk.into(),
151            tx_clk.into(),
152            mdio.into(),
153            mdc.into(),
154            rxdv.into(),
155            rx_d0.into(),
156            rx_d1.into(),
157            rx_d2.into(),
158            rx_d3.into(),
159            tx_d0.into(),
160            tx_d1.into(),
161            tx_d2.into(),
162            tx_d3.into(),
163            tx_en.into(),
164        ]);
165
166        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
167    }
168
169    fn new_inner<const TX: usize, const RX: usize>(
170        queue: &'d mut PacketQueue<TX, RX>,
171        peri: Peri<'d, T>,
172        _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
173        pins: Pins<'d>,
174        phy: P,
175        mac_addr: [u8; 6],
176    ) -> Self {
177        let dma = T::regs().ethernet_dma();
178        let mac = T::regs().ethernet_mac();
179        let mtl = T::regs().ethernet_mtl();
180
181        // Reset and wait
182        dma.dmamr().modify(|w| w.set_swr(true));
183        while dma.dmamr().read().swr() {}
184
185        mac.maccr().modify(|w| {
186            w.set_ipg(0b000); // 96 bit times
187            w.set_acs(true);
188            w.set_fes(true);
189            w.set_dm(true);
190            // TODO: Carrier sense ? ECRSFD
191        });
192
193        // Disable multicast filter
194        mac.macpfr().modify(|w| w.set_pm(true));
195
196        // Note: Writing to LR triggers synchronisation of both LR and HR into the MAC core,
197        // so the LR write must happen after the HR write.
198        mac.maca0hr()
199            .modify(|w| w.set_addrhi(u16::from(mac_addr[4]) | (u16::from(mac_addr[5]) << 8)));
200        mac.maca0lr().write(|w| {
201            w.set_addrlo(
202                u32::from(mac_addr[0])
203                    | (u32::from(mac_addr[1]) << 8)
204                    | (u32::from(mac_addr[2]) << 16)
205                    | (u32::from(mac_addr[3]) << 24),
206            )
207        });
208
209        mac.macqtx_fcr().modify(|w| w.set_pt(0x100));
210
211        // disable all MMC RX interrupts
212        mac.mmc_rx_interrupt_mask().write(|w| {
213            w.set_rxcrcerpim(true);
214            w.set_rxalgnerpim(true);
215            w.set_rxucgpim(true);
216            w.set_rxlpiuscim(true);
217            w.set_rxlpitrcim(true)
218        });
219
220        // disable all MMC TX interrupts
221        mac.mmc_tx_interrupt_mask().write(|w| {
222            w.set_txscolgpim(true);
223            w.set_txmcolgpim(true);
224            w.set_txgpktim(true);
225            w.set_txlpiuscim(true);
226            w.set_txlpitrcim(true);
227        });
228
229        mtl.mtlrx_qomr().modify(|w| w.set_rsf(true));
230        mtl.mtltx_qomr().modify(|w| w.set_tsf(true));
231
232        dma.dmactx_cr().modify(|w| w.set_txpbl(1)); // 32 ?
233        dma.dmacrx_cr().modify(|w| {
234            w.set_rxpbl(1); // 32 ?
235            w.set_rbsz(RX_BUFFER_SIZE as u16);
236        });
237
238        let hclk = <T as SealedRccPeripheral>::frequency();
239        let hclk_mhz = hclk.0 / 1_000_000;
240
241        // Set the MDC clock frequency in the range 1MHz - 2.5MHz
242        let clock_range = match hclk_mhz {
243            0..=34 => 2,    // Divide by 16
244            35..=59 => 3,   // Divide by 26
245            60..=99 => 0,   // Divide by 42
246            100..=149 => 1, // Divide by 62
247            150..=249 => 4, // Divide by 102
248            250..=310 => 5, // Divide by 124
249            _ => {
250                panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
251            }
252        };
253
254        let mut this = Self {
255            _peri: peri,
256            tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
257            rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
258            pins,
259            phy,
260            station_management: EthernetStationManagement {
261                peri: PhantomData,
262                clock_range: clock_range,
263            },
264            mac_addr,
265        };
266
267        fence(Ordering::SeqCst);
268
269        let mac = T::regs().ethernet_mac();
270        let mtl = T::regs().ethernet_mtl();
271        let dma = T::regs().ethernet_dma();
272
273        mac.maccr().modify(|w| {
274            w.set_re(true);
275            w.set_te(true);
276        });
277        mtl.mtltx_qomr().modify(|w| w.set_ftq(true));
278
279        dma.dmactx_cr().modify(|w| w.set_st(true));
280        dma.dmacrx_cr().modify(|w| w.set_sr(true));
281
282        // Enable interrupts
283        dma.dmacier().modify(|w| {
284            w.set_nie(true);
285            w.set_rie(true);
286            w.set_tie(true);
287        });
288
289        this.phy.phy_reset(&mut this.station_management);
290        this.phy.phy_init(&mut this.station_management);
291
292        interrupt::ETH.unpend();
293        unsafe { interrupt::ETH.enable() };
294
295        this
296    }
297}
298
299/// Ethernet SMI driver.
300pub struct EthernetStationManagement<T: Instance> {
301    peri: PhantomData<T>,
302    clock_range: u8,
303}
304
305impl<T: Instance> StationManagement for EthernetStationManagement<T> {
306    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
307        let mac = T::regs().ethernet_mac();
308
309        mac.macmdioar().modify(|w| {
310            w.set_pa(phy_addr);
311            w.set_rda(reg);
312            w.set_goc(0b11); // read
313            w.set_cr(self.clock_range);
314            w.set_mb(true);
315        });
316        while mac.macmdioar().read().mb() {}
317        mac.macmdiodr().read().md()
318    }
319
320    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
321        let mac = T::regs().ethernet_mac();
322
323        mac.macmdiodr().write(|w| w.set_md(val));
324        mac.macmdioar().modify(|w| {
325            w.set_pa(phy_addr);
326            w.set_rda(reg);
327            w.set_goc(0b01); // write
328            w.set_cr(self.clock_range);
329            w.set_mb(true);
330        });
331        while mac.macmdioar().read().mb() {}
332    }
333}
334
335impl<'d, T: Instance, P: Phy> Drop for Ethernet<'d, T, P> {
336    fn drop(&mut self) {
337        let dma = T::regs().ethernet_dma();
338        let mac = T::regs().ethernet_mac();
339        let mtl = T::regs().ethernet_mtl();
340
341        // Disable the TX DMA and wait for any previous transmissions to be completed
342        dma.dmactx_cr().modify(|w| w.set_st(false));
343        while {
344            let txqueue = mtl.mtltx_qdr().read();
345            txqueue.trcsts() == 0b01 || txqueue.txqsts()
346        } {}
347
348        // Disable MAC transmitter and receiver
349        mac.maccr().modify(|w| {
350            w.set_re(false);
351            w.set_te(false);
352        });
353
354        // Wait for previous receiver transfers to be completed and then disable the RX DMA
355        while {
356            let rxqueue = mtl.mtlrx_qdr().read();
357            rxqueue.rxqsts() != 0b00 || rxqueue.prxq() != 0
358        } {}
359        dma.dmacrx_cr().modify(|w| w.set_sr(false));
360
361        critical_section::with(|_| {
362            for pin in match self.pins {
363                Pins::Rmii(ref mut pins) => pins.iter_mut(),
364                Pins::Mii(ref mut pins) => pins.iter_mut(),
365            } {
366                pin.set_as_disconnected();
367            }
368        })
369    }
370}
embassy_stm32/eth/v2/mod.rs

embassy_stm32/eth/v2/
mod.rs
