embassy_stm32_plus/builder/spi/spi2/
rx.rs

1use embassy_stm32::mode::{Async, Blocking};
2use embassy_stm32::peripherals::{DMA1_CH4, DMA1_CH5, PB13, PB14, SPI2};
3use embassy_stm32::spi::{Config, Spi};
4use crate::builder::spi::base::SpiBase;
5
6/// spi2 rx builder
7pub struct Spi2RxBuilder {
8    /// spi device
9    pub base: SpiBase<SPI2>,
10    /// sck pin
11    pub sck: PB13,
12    /// miso pin
13    pub miso: PB14,
14}
15
16/// custom method
17impl Spi2RxBuilder {
18    /// create builder
19    #[inline]
20    pub fn new(spi: SPI2, sck: PB13, miso: PB14) -> Self {
21        Self { base: SpiBase::new(spi), sck, miso }
22    }
23
24    /// set spi config
25    #[inline]
26    pub fn config(mut self, config: Config) -> Self {
27        self.base.set_config(config);
28        self
29    }
30
31    /// Create a new SPI driver, in RX-only mode (only MISO pin, no MOSI).<br />
32    /// more see [`Spi::<Async>::new_rxonly`]
33    #[inline]
34    pub fn build(self, tx_dma: DMA1_CH5, rx_dma: DMA1_CH4) -> Spi<'static, Async> {
35        Spi::new_rxonly(self.base.spi, self.sck, self.miso, tx_dma, rx_dma, self.base.config.unwrap_or_default())
36    }
37
38    /// Create a new blocking SPI driver, in RX-only mode (only MISO pin, no MOSI).<br />
39    /// more see [`Spi::<Blocking>::new_blocking_rxonly`]
40    #[inline]
41    pub fn build_blocking(self) -> Spi<'static, Blocking> {
42        Spi::new_blocking_rxonly(self.base.spi, self.sck, self.miso, self.base.config.unwrap_or_default())
43    }
44}
embassy_stm32_plus/builder/spi/spi2/rx.rs

embassy_stm32_plus/builder/spi/spi2/
rx.rs
