embassy_stm32_plus/builder/uart/uart2/
mod.rs

1use embassy_stm32::{bind_interrupts, Peripheral, usart};
2use embassy_stm32::mode::Async;
3#[cfg(not(STM32C0))]
4use embassy_stm32::peripherals::{DMA1_CH6, DMA1_CH7};
5use embassy_stm32::peripherals::USART2;
6use embassy_stm32::usart::{Config, ConfigError, RtsPin, RxPin, TxPin, Uart};
7#[cfg(STM32C0)]
8use embassy_stm32::usart::{RxDma, TxDma};
9use crate::builder::uart::base::UartBase;
10use crate::builder::uart::uart2::rx::{Uart2Rts, Uart2Rx, Uart2RxBuilder};
11use crate::builder::uart::uart2::tx::{Uart2Cts, Uart2Tx};
12
13pub mod rx;
14pub mod tx;
15
16bind_interrupts!(struct Irqs {
17    USART2 => usart::InterruptHandler<USART2>;
18});
19
20/// uart2 builder
21pub struct Uart2Builder {
22    /// uart2 base data
23    pub base: UartBase<USART2>,
24    /// uart2 tx pin
25    pub tx: Uart2Tx,
26    /// uart2 rx pin
27    pub rx: Uart2Rx,
28    /// use rts cts
29    pub rts_cts: Option<(Uart2Rts, Uart2Cts)>,
30}
31
32/// uart2 build
33macro_rules! uart2_build {
34    ($tx_dma:ty,$rx_dma:ty) => {
35        /// build a serial port that supports read and write data
36        pub fn build(self, tx_dma: $tx_dma, rx_dma: $rx_dma) -> Result<Uart<'static, Async>, ConfigError> {
37            let rx = Uart2RxBuilder { base: self.base, rx: self.rx, rts: None };
38            match self.tx {
39                Uart2Tx::PA2(pa2) => { Self::build_rx(pa2, rx, tx_dma, rx_dma, self.rts_cts) }
40                #[cfg(USART2_TX_PA4)]
41                Uart2Tx::PA4(pa4) => { Self::build_rx(pa4, rx, tx_dma, rx_dma, self.rts_cts) }
42                #[cfg(USART2_PA8)]
43                Uart2Tx::PA8(pa8) => { Self::build_rx(pa8, rx, tx_dma, rx_dma, self.rts_cts) }
44                #[cfg(USART2_PA14)]
45                Uart2Tx::PA14(pa14) => { Self::build_rx(pa14, rx, tx_dma, rx_dma, self.rts_cts) }
46                #[cfg(USART2_PD5)]
47                Uart2Tx::PD5(pd5) => { Self::build_rx(pd5, rx, tx_dma, rx_dma, self.rts_cts) }
48            }
49        }
50
51        /// build by rx
52        fn build_rx(
53            tx: impl Peripheral<P=impl TxPin<USART2>> + 'static,
54            rx: Uart2RxBuilder,
55            tx_dma: $tx_dma,
56            rx_dma: $rx_dma,
57            rts_cts: Option<(Uart2Rts, Uart2Cts)>)
58            -> Result<Uart<'static, Async>, ConfigError> {
59            match rx.rx {
60                #[cfg(USART2_PA3)]
61                Uart2Rx::PA3(pa3) => { Self::build_rts(tx, pa3, rx.base, tx_dma, rx_dma, rts_cts) }
62                #[cfg(USART2_PA5)]
63                Uart2Rx::PA5(pa5) => { Self::build_rts(tx, pa5, rx.base, tx_dma, rx_dma, rts_cts) }
64                #[cfg(USART2_PA13)]
65                Uart2Rx::PA13(pa13) => { Self::build_rts(tx, pa13, rx.base, tx_dma, rx_dma, rts_cts) }
66                #[cfg(USART2_PA14)]
67                Uart2Rx::PA14(pa14) => { Self::build_rts(tx, pa14, rx.base, tx_dma, rx_dma, rts_cts) }
68                #[cfg(USART2_PA15)]
69                Uart2Rx::PA15(pa15) => { Self::build_rts(tx, pa15, rx.base, tx_dma, rx_dma, rts_cts) }
70                #[cfg(USART2_PD6)]
71                Uart2Rx::PD6(pd6) => { Self::build_rts(tx, pd6, rx.base, tx_dma, rx_dma, rts_cts) }
72            }
73        }
74
75        /// build by rts
76        fn build_rts(
77            tx: impl Peripheral<P=impl TxPin<USART2>> + 'static,
78            rx: impl Peripheral<P=impl RxPin<USART2>> + 'static,
79            base: UartBase<USART2>,
80            tx_dma: $tx_dma,
81            rx_dma: $rx_dma,
82            rts_cts: Option<(Uart2Rts, Uart2Cts)>)
83            -> Result<Uart<'static, Async>, ConfigError> {
84            let (rts, cts) = crate::match_some_return!(rts_cts,
85                Uart::new(base.uart, rx, tx, Irqs, tx_dma, rx_dma, base.config.unwrap_or_default()));
86            match rts {
87                Uart2Rts::PA1(pa1) => { Self::build_cts(tx, rx, base, tx_dma, rx_dma, pa1, cts) }
88                #[cfg(USART2_PB9)]
89                Uart2Rts::PB9(pb9) => { Self::build_cts(tx, rx, base, tx_dma, rx_dma, pb9, cts) }
90                #[cfg(USART2_PC14)]
91                Uart2Rts::PC14(pc14) => { Self::build_cts(tx, rx, base, tx_dma, rx_dma, pc14, cts) }
92                #[cfg(USART2_PD4)]
93                Uart2Rts::PD4(pd4) => { Self::build_cts(tx, rx, base, tx_dma, rx_dma, pd4, cts) }
94            }
95        }
96
97        /// build by cts
98        fn build_cts(
99            tx: impl Peripheral<P=impl TxPin<USART2>> + 'static,
100            rx: impl Peripheral<P=impl RxPin<USART2>> + 'static,
101            base: UartBase<USART2>,
102            tx_dma: $tx_dma,
103            rx_dma: $rx_dma,
104            rts: impl Peripheral<P=impl RtsPin<USART2>> + 'static,
105            cts: Uart2Cts)
106            -> Result<Uart<'static, Async>, ConfigError> {
107            match cts {
108                Uart2Cts::PA0(pa0) => { Uart::new_with_rtscts(base.uart, rx, tx, Irqs, rts, pa0, tx_dma, rx_dma, base.config.unwrap_or_default()) }
109                #[cfg(USART2_PB7)]
110                Uart2Cts::PB7(pb7) => { Uart::new_with_rtscts(base.uart, rx, tx, Irqs, rts, pb7, tx_dma, rx_dma, base.config.unwrap_or_default()) }
111                #[cfg(USART2_PB8)]
112                Uart2Cts::PB8(pb8) => { Uart::new_with_rtscts(base.uart, rx, tx, Irqs, rts, pb8, tx_dma, rx_dma, base.config.unwrap_or_default()) }
113                #[cfg(USART2_PD3)]
114                Uart2Cts::PD3(pd3) => { Uart::new_with_rtscts(base.uart, rx, tx, Irqs, rts, pd3, tx_dma, rx_dma, base.config.unwrap_or_default()) }
115            }
116        }
117    };
118}
119
120/// custom method
121impl Uart2Builder {
122    /// create builder
123    #[inline]
124    pub fn new(uart: USART2, tx: Uart2Tx, rx: Uart2Rx) -> Self {
125        Self { base: UartBase::new(uart), tx, rx, rts_cts: None }
126    }
127
128    /// set uart config
129    #[inline]
130    pub fn config(mut self, config: Config) -> Self {
131        self.base.set_config(config);
132        self
133    }
134
135    /// set rts cts
136    #[inline]
137    pub fn rts_cts(mut self, rts: Uart2Rts, cts: Uart2Cts) -> Self {
138        self.rts_cts = Some((rts, cts));
139        self
140    }
141
142    #[cfg(STM32C0)]
143    uart2_build!(impl Peripheral<P = impl TxDma<USART2>> + 'static,impl Peripheral<P = impl RxDma<USART2>> + 'static);
144    #[cfg(not(STM32C0))]
145    uart2_build!(DMA1_CH7,DMA1_CH6);
146}
embassy_stm32_plus/builder/uart/uart2/mod.rs

embassy_stm32_plus/builder/uart/uart2/
mod.rs
