embassy_stm32_plus/builder/spi/spi3/
mod.rs

1use embassy_stm32::mode::{Async, Blocking};
2use embassy_stm32::Peripheral;
3use embassy_stm32::peripherals::{DMA2_CH1, DMA2_CH2, PB3, SPI3};
4#[cfg(SPI3_PC10)]
5use embassy_stm32::peripherals::PC10;
6use embassy_stm32::spi::{Config, MisoPin, MosiPin, Spi};
7use crate::builder::spi::base::SpiBase;
8use crate::builder::spi::spi3::rx::{Spi3Miso, Spi3RxBuilder};
9use crate::builder::spi::spi3::tx::Spi3Mosi;
10
11pub mod rx;
12pub mod tx;
13
14/// spi3 sck pin
15pub enum Spi3Sck {
16    PB3(PB3),
17    #[cfg(SPI3_PC10)]
18    PC10(PC10),
19}
20
21/// spi3 builder
22pub struct Spi3Builder {
23    /// spi device
24    pub base: SpiBase<SPI3>,
25    /// sck pin
26    pub sck: Spi3Sck,
27    /// mosi pin
28    pub mosi: Spi3Mosi,
29    /// miso pin
30    pub miso: Spi3Miso,
31}
32
33/// custom method
34impl Spi3Builder {
35    /// create builder
36    #[inline]
37    pub fn new(spi: SPI3, sck: Spi3Sck, mosi: Spi3Mosi, miso: Spi3Miso) -> Self {
38        Self { base: SpiBase::new(spi), sck, mosi, miso }
39    }
40
41    /// set spi config
42    #[inline]
43    pub fn config(mut self, config: Config) -> Self {
44        self.base.set_config(config);
45        self
46    }
47
48    /// Create a new SPI driver.<br />
49    /// more see [`Spi::<Async>::new`]
50    #[inline]
51    pub fn build(self, tx_dma: DMA2_CH2, rx_dma: DMA2_CH1) -> Spi<'static, Async> {
52        let Self { base, sck, mosi, miso } = self;
53        let rx = Spi3RxBuilder { base, sck, miso };
54        match mosi {
55            Spi3Mosi::PB5(pb5) => { Self::build_rx(rx, pb5, tx_dma, rx_dma) }
56            #[cfg(SPI3_PC12)]
57            Spi3Mosi::PC12(pc12) => { Self::build_rx(rx, pc12, tx_dma, rx_dma) }
58        }
59    }
60
61    /// build by rx
62    fn build_rx(
63        rx: Spi3RxBuilder,
64        mosi: impl Peripheral<P=impl MosiPin<SPI3>> + 'static,
65        tx_dma: DMA2_CH2,
66        rx_dma: DMA2_CH1) -> Spi<'static, Async> {
67        let Spi3RxBuilder { base, sck, miso } = rx;
68        match miso {
69            Spi3Miso::PB4(pb4) => { Self::build_sck(base, sck, mosi, pb4, tx_dma, rx_dma) }
70            #[cfg(SPI3_PC11)]
71            Spi3Miso::PC11(pc11) => { Self::build_sck(base, sck, mosi, pc11, tx_dma, rx_dma) }
72        }
73    }
74
75    /// build by sck
76    fn build_sck(
77        base: SpiBase<SPI3>,
78        sck: Spi3Sck,
79        mosi: impl Peripheral<P=impl MosiPin<SPI3>> + 'static,
80        miso: impl Peripheral<P=impl MisoPin<SPI3>> + 'static,
81        tx_dma: DMA2_CH2,
82        rx_dma: DMA2_CH1) -> Spi<'static, Async> {
83        match sck {
84            Spi3Sck::PB3(pb3) => { Spi::new(base.spi, pb3, mosi, miso, tx_dma, rx_dma, base.config.unwrap_or_default()) }
85            #[cfg(SPI3_PC10)]
86            Spi3Sck::PC10(pc10) => { Spi::new(base.spi, pc10, mosi, miso, tx_dma, rx_dma, base.config.unwrap_or_default()) }
87        }
88    }
89
90    /// Create a new blocking SPI driver.<br />
91    /// more see [`Spi::<Blocking>::new_blocking`]
92    #[inline]
93    pub fn build_blocking(self) -> Spi<'static, Blocking> {
94        let Self { base, sck, mosi, miso } = self;
95        let rx = Spi3RxBuilder { base, sck, miso };
96        match mosi {
97            Spi3Mosi::PB5(pb5) => { Self::build_blocking_rx(rx, pb5) }
98            #[cfg(SPI3_PC12)]
99            Spi3Mosi::PC12(pc12) => { Self::build_blocking_rx(rx, pc12) }
100        }
101    }
102
103    /// build blocking by rx
104    fn build_blocking_rx(rx: Spi3RxBuilder, mosi: impl Peripheral<P=impl MosiPin<SPI3>> + 'static) -> Spi<'static, Blocking> {
105        let Spi3RxBuilder { base, sck, miso } = rx;
106        match miso {
107            Spi3Miso::PB4(pb4) => { Self::build_blocking_sck(base, sck, mosi, pb4) }
108            #[cfg(SPI3_PC11)]
109            Spi3Miso::PC11(pc11) => { Self::build_blocking_sck(base, sck, mosi, pc11) }
110        }
111    }
112
113    /// build blocking by sck
114    fn build_blocking_sck(
115        base: SpiBase<SPI3>,
116        sck: Spi3Sck,
117        mosi: impl Peripheral<P=impl MosiPin<SPI3>> + 'static,
118        miso: impl Peripheral<P=impl MisoPin<SPI3>> + 'static) -> Spi<'static, Blocking> {
119        match sck {
120            Spi3Sck::PB3(pb3) => { Spi::new_blocking(base.spi, pb3, mosi, miso, base.config.unwrap_or_default()) }
121            #[cfg(SPI3_PC10)]
122            Spi3Sck::PC10(pc10) => { Spi::new_blocking(base.spi, pc10, mosi, miso, base.config.unwrap_or_default()) }
123        }
124    }
125}
embassy_stm32_plus/builder/spi/spi3/mod.rs

embassy_stm32_plus/builder/spi/spi3/
mod.rs
