embassy_stm32_plus/builder/uart/uart3/
mod.rs1use embassy_stm32::{bind_interrupts, Peripheral, usart};
2use embassy_stm32::mode::Async;
3use embassy_stm32::peripherals::{DMA1_CH2, DMA1_CH3, USART3};
4use embassy_stm32::usart::{Config, ConfigError, RtsPin, RxPin, TxPin, Uart};
5use crate::builder::uart::base::UartBase;
6use crate::builder::uart::uart3::rx::{Uart3Rts, Uart3Rx, Uart3RxBuilder};
7use crate::builder::uart::uart3::tx::{Uart3Cts, Uart3Tx};
8
9pub mod rx;
10pub mod tx;
11
12bind_interrupts!(struct Irqs {
13 USART3 => usart::InterruptHandler<USART3>;
14});
15
16pub struct Uart3Builder {
18 pub base: UartBase<USART3>,
20 pub tx: Uart3Tx,
22 pub rx: Uart3Rx,
24 pub rts_cts: Option<(Uart3Rts, Uart3Cts)>,
26}
27
28impl Uart3Builder {
30 #[inline]
32 pub fn new(uart: USART3, tx: Uart3Tx, rx: Uart3Rx) -> Self {
33 Self { base: UartBase::new(uart), tx, rx, rts_cts: None }
34 }
35
36 #[inline]
38 pub fn config(mut self, config: Config) -> Self {
39 self.base.set_config(config);
40 self
41 }
42
43 #[inline]
45 pub fn rts_cts(mut self, rts: Uart3Rts, cts: Uart3Cts) -> Self {
46 self.rts_cts = Some((rts, cts));
47 self
48 }
49
50 pub fn build(self, tx_dma: DMA1_CH2, rx_dma: DMA1_CH3) -> Result<Uart<'static, Async>, ConfigError> {
52 let rx = Uart3RxBuilder { base: self.base, rx: self.rx, rts: None };
53 match self.tx {
54 Uart3Tx::PB10(pb10) => { Self::build_rx(pb10, rx, tx_dma, rx_dma, self.rts_cts) }
55 #[cfg(PC10)]
56 Uart3Tx::PC10(pc10) => { Self::build_rx(pc10, rx, tx_dma, rx_dma, self.rts_cts) }
57 #[cfg(PD8)]
58 Uart3Tx::PD8(pd8) => { Self::build_rx(pd8, rx, tx_dma, rx_dma, self.rts_cts) }
59 }
60 }
61
62 fn build_rx(
64 tx: impl Peripheral<P=impl TxPin<USART3>> + 'static,
65 rx: Uart3RxBuilder,
66 tx_dma: DMA1_CH2,
67 rx_dma: DMA1_CH3,
68 rts_cts: Option<(Uart3Rts, Uart3Cts)>)
69 -> Result<Uart<'static, Async>, ConfigError> {
70 match rx.rx {
71 Uart3Rx::PB11(pb11) => { Self::build_rts(tx, pb11, rx.base, tx_dma, rx_dma, rts_cts) }
72 #[cfg(PC11)]
73 Uart3Rx::PC11(pc11) => { Self::build_rts(tx, pc11, rx.base, tx_dma, rx_dma, rts_cts) }
74 #[cfg(PD9)]
75 Uart3Rx::PD9(pd9) => { Self::build_rts(tx, pd9, rx.base, tx_dma, rx_dma, rts_cts) }
76 }
77 }
78
79 fn build_rts(
81 tx: impl Peripheral<P=impl TxPin<USART3>> + 'static,
82 rx: impl Peripheral<P=impl RxPin<USART3>> + 'static,
83 base: UartBase<USART3>,
84 tx_dma: DMA1_CH2,
85 rx_dma: DMA1_CH3,
86 rts_cts: Option<(Uart3Rts, Uart3Cts)>)
87 -> Result<Uart<'static, Async>, ConfigError> {
88 let (rts, cts) = crate::match_some_return!(rts_cts,
89 Uart::new(base.uart, rx, tx, Irqs, tx_dma, rx_dma, base.config.unwrap_or_default()));
90
91 match rts {
92 Uart3Rts::PB14(pb14) => { Self::build_cts(tx, rx, base, tx_dma, rx_dma, pb14, cts) }
93 #[cfg(PD12)]
94 Uart3Rts::PD12(pd12) => { Self::build_cts(tx, rx, base, tx_dma, rx_dma, pd12, cts) }
95 }
96 }
97
98 fn build_cts(
100 tx: impl Peripheral<P=impl TxPin<USART3>> + 'static,
101 rx: impl Peripheral<P=impl RxPin<USART3>> + 'static,
102 base: UartBase<USART3>,
103 tx_dma: DMA1_CH2,
104 rx_dma: DMA1_CH3,
105 rts: impl Peripheral<P=impl RtsPin<USART3>> + 'static,
106 cts: Uart3Cts)
107 -> Result<Uart<'static, Async>, ConfigError> {
108 match cts {
109 Uart3Cts::PB13(pb13) => {
110 Uart::new_with_rtscts(base.uart, rx, tx, Irqs, rts, pb13, tx_dma, rx_dma, base.config.unwrap_or_default())
111 }
112 #[cfg(PD11)]
113 Uart3Cts::PD11(pd11) => {
114 Uart::new_with_rtscts(base.uart, rx, tx, Irqs, rts, pd11, tx_dma, rx_dma, base.config.unwrap_or_default())
115 }
116 }
117 }
118}