embassy_stm32_plus/builder/spi/spi3/
rx.rs

1use embassy_stm32::mode::{Async, Blocking};
2use embassy_stm32::Peripheral;
3use embassy_stm32::peripherals::{DMA2_CH1, DMA2_CH2, PB4, SPI3};
4#[cfg(SPI3_PC11)]
5use embassy_stm32::peripherals::PC11;
6use embassy_stm32::spi::{Config, SckPin, Spi};
7use crate::builder::spi::base::SpiBase;
8use crate::builder::spi::spi3::Spi3Sck;
9
10/// spi3 miso pin
11pub enum Spi3Miso {
12    PB4(PB4),
13    #[cfg(SPI3_PC11)]
14    PC11(PC11),
15}
16
17/// spi3 rx builder
18pub struct Spi3RxBuilder {
19    /// spi device
20    pub base: SpiBase<SPI3>,
21    /// sck pin
22    pub sck: Spi3Sck,
23    /// miso pin
24    pub miso: Spi3Miso,
25}
26
27/// custom method
28impl Spi3RxBuilder {
29    /// create builder
30    #[inline]
31    pub fn new(spi: SPI3, sck: Spi3Sck, miso: Spi3Miso) -> Self {
32        Self { base: SpiBase::new(spi), sck, miso }
33    }
34
35    /// set spi config
36    #[inline]
37    pub fn config(mut self, config: Config) -> Self {
38        self.base.set_config(config);
39        self
40    }
41
42    /// Create a new SPI driver, in RX-only mode (only MISO pin, no MOSI).<br />
43    /// more see [`Spi::<Async>::new_rxonly`]
44    #[inline]
45    pub fn build(self, tx_dma: DMA2_CH2, rx_dma: DMA2_CH1) -> Spi<'static, Async> {
46        let Self { base, sck, miso } = self;
47        match sck {
48            Spi3Sck::PB3(pb3) => { Self::build_miso(base, pb3, miso, tx_dma, rx_dma) }
49            #[cfg(SPI3_PC10)]
50            Spi3Sck::PC10(pc10) => { Self::build_miso(base, pc10, miso, tx_dma, rx_dma) }
51        }
52    }
53
54    /// build by miso
55    fn build_miso(
56        base: SpiBase<SPI3>,
57        sck: impl Peripheral<P=impl SckPin<SPI3>> + 'static,
58        miso: Spi3Miso,
59        tx_dma: DMA2_CH2,
60        rx_dma: DMA2_CH1) -> Spi<'static, Async> {
61        match miso {
62            Spi3Miso::PB4(pb4) => { Spi::new_rxonly(base.spi, sck, pb4, tx_dma, rx_dma, base.config.unwrap_or_default()) }
63            #[cfg(SPI3_PC11)]
64            Spi3Miso::PC11(pc11) => { Spi::new_rxonly(base.spi, sck, pc11, tx_dma, rx_dma, base.config.unwrap_or_default()) }
65        }
66    }
67
68    /// Create a new blocking SPI driver, in RX-only mode (only MISO pin, no MOSI).<br />
69    /// more see [`Spi::<Blocking>::new_blocking_rxonly`]
70    #[inline]
71    pub fn build_blocking(self) -> Spi<'static, Blocking> {
72        let Self { base, sck, miso } = self;
73        match sck {
74            Spi3Sck::PB3(pb3) => { Self::build_blocking_miso(base, pb3, miso) }
75            #[cfg(SPI3_PC10)]
76            Spi3Sck::PC10(pc10) => { Self::build_blocking_miso(base, pc10, miso) }
77        }
78    }
79
80    /// build blocking by miso
81    fn build_blocking_miso(
82        base: SpiBase<SPI3>,
83        sck: impl Peripheral<P=impl SckPin<SPI3>> + 'static,
84        miso: Spi3Miso) -> Spi<'static, Blocking> {
85        match miso {
86            Spi3Miso::PB4(pb4) => { Spi::new_blocking_rxonly(base.spi, sck, pb4, base.config.unwrap_or_default()) }
87            #[cfg(SPI3_PC11)]
88            Spi3Miso::PC11(pc11) => { Spi::new_blocking_rxonly(base.spi, sck, pc11, base.config.unwrap_or_default()) }
89        }
90    }
91}
embassy_stm32_plus/builder/spi/spi3/rx.rs

embassy_stm32_plus/builder/spi/spi3/
rx.rs
