embassy_stm32_plus/builder/spi/spi1/
rx.rs

1use embassy_stm32::mode::{Async, Blocking};
2use embassy_stm32::Peripheral;
3#[cfg(not(STM32C0))]
4use embassy_stm32::peripherals::{DMA1_CH2, DMA1_CH3};
5use embassy_stm32::peripherals::SPI1;
6#[cfg(SPI1_PA11)]
7use embassy_stm32::peripherals::PA11;
8#[cfg(SPI1_PA6)]
9use embassy_stm32::peripherals::PA6;
10#[cfg(SPI1_PB4)]
11use embassy_stm32::peripherals::PB4;
12#[cfg(SPI1_PB6)]
13use embassy_stm32::peripherals::PB6;
14use embassy_stm32::spi::{Config, SckPin, Spi};
15#[cfg(STM32C0)]
16use embassy_stm32::spi::{RxDma, TxDma};
17use crate::builder::spi::base::SpiBase;
18use crate::builder::spi::spi1::Spi1Sck;
19
20/// spi1 miso pin
21pub enum Spi1Miso {
22    #[cfg(SPI1_PA6)]
23    PA6(PA6),
24    #[cfg(SPI1_PA11)]
25    PA11(PA11),
26    #[cfg(SPI1_PB4)]
27    PB4(PB4),
28    #[cfg(SPI1_PB6)]
29    PB6(PB6),
30}
31
32/// spi1 rx builder
33pub struct Spi1RxBuilder {
34    /// spi device
35    pub base: SpiBase<SPI1>,
36    /// sck pin
37    pub sck: Spi1Sck,
38    /// miso pin
39    pub miso: Spi1Miso,
40}
41
42/// spi1 rx build
43macro_rules! spi1_rx_build {
44    ($tx_dma:ty,$rx_dma:ty) => {
45        /// Create a new SPI driver, in RX-only mode (only MISO pin, no MOSI).<br />
46        /// more see [`Spi::<Async>::new_rxonly`]
47        pub fn build(self, tx_dma: $tx_dma, rx_dma: $rx_dma) -> Spi<'static, Async> {
48            let Self { base, sck, miso } = self;
49            match sck {
50                #[cfg(SPI1_PA1)]
51                Spi1Sck::PA1(pa1) => { Self::build_miso(base, pa1, miso, tx_dma, rx_dma) }
52                #[cfg(SPI1_PA5)]
53                Spi1Sck::PA5(pa5) => { Self::build_miso(base, pa5, miso, tx_dma, rx_dma) }
54                #[cfg(SPI1_PB3)]
55                Spi1Sck::PB3(pb3) => { Self::build_miso(base, pb3, miso, tx_dma, rx_dma) }
56                #[cfg(SPI1_PB6)]
57                Spi1Sck::PB6(pb6) => { Self::build_miso(base, pb6, miso, tx_dma, rx_dma) }
58            }
59        }
60
61        /// build by miso
62        fn build_miso(
63            base: SpiBase<SPI1>,
64            sck: impl Peripheral<P=impl SckPin<SPI1>> + 'static,
65            miso: Spi1Miso,
66            tx_dma: $tx_dma,
67            rx_dma: $rx_dma) -> Spi<'static, Async> {
68            match miso {
69                #[cfg(SPI1_PA6)]
70                Spi1Miso::PA6(pa6) => { Spi::new_rxonly(base.spi, sck, pa6, tx_dma, rx_dma, base.config.unwrap_or_default()) }
71                #[cfg(SPI1_PA11)]
72                Spi1Miso::PA11(pa11) => { Spi::new_rxonly(base.spi, sck, pa11, tx_dma, rx_dma, base.config.unwrap_or_default()) }
73                #[cfg(SPI1_PB4)]
74                Spi1Miso::PB4(pb4) => { Spi::new_rxonly(base.spi, sck, pb4, tx_dma, rx_dma, base.config.unwrap_or_default()) }
75                #[cfg(SPI1_PB6)]
76                Spi1Miso::PB6(pb6) => { Spi::new_rxonly(base.spi, sck, pb6, tx_dma, rx_dma, base.config.unwrap_or_default()) }
77            }
78        }
79    };
80}
81
82/// custom method
83impl Spi1RxBuilder {
84    /// create builder
85    #[inline]
86    pub fn new(spi: SPI1, sck: Spi1Sck, miso: Spi1Miso) -> Self {
87        Self { base: SpiBase::new(spi), sck, miso }
88    }
89
90    /// set spi config
91    #[inline]
92    pub fn config(mut self, config: Config) -> Self {
93        self.base.set_config(config);
94        self
95    }
96
97    /// Create a new blocking SPI driver, in RX-only mode (only MISO pin, no MOSI).<br />
98    /// more see [`Spi::<Blocking>::new_blocking_rxonly`]
99    pub fn build_blocking(self) -> Spi<'static, Blocking> {
100        let Self { base, sck, miso } = self;
101        match sck {
102            #[cfg(SPI1_PA1)]
103            Spi1Sck::PA1(pa1) => { Self::build_blocking_miso(base, pa1, miso) }
104            #[cfg(SPI1_PA5)]
105            Spi1Sck::PA5(pa5) => { Self::build_blocking_miso(base, pa5, miso) }
106            #[cfg(SPI1_PB3)]
107            Spi1Sck::PB3(pb3) => { Self::build_blocking_miso(base, pb3, miso) }
108            #[cfg(SPI1_PB6)]
109            Spi1Sck::PB6(pb6) => { Self::build_blocking_miso(base, pb6, miso) }
110        }
111    }
112
113    /// build blocking by miso
114    fn build_blocking_miso(
115        base: SpiBase<SPI1>,
116        sck: impl Peripheral<P=impl SckPin<SPI1>> + 'static,
117        miso: Spi1Miso) -> Spi<'static, Blocking> {
118        match miso {
119            #[cfg(SPI1_PA6)]
120            Spi1Miso::PA6(pa6) => { Spi::new_blocking_rxonly(base.spi, sck, pa6, base.config.unwrap_or_default()) }
121            #[cfg(SPI1_PA11)]
122            Spi1Miso::PA11(pa11) => { Spi::new_blocking_rxonly(base.spi, sck, pa11, base.config.unwrap_or_default()) }
123            #[cfg(SPI1_PB4)]
124            Spi1Miso::PB4(pb4) => { Spi::new_blocking_rxonly(base.spi, sck, pb4, base.config.unwrap_or_default()) }
125            #[cfg(SPI1_PB6)]
126            Spi1Miso::PB6(pb6) => { Spi::new_blocking_rxonly(base.spi, sck, pb6, base.config.unwrap_or_default()) }
127        }
128    }
129
130    #[cfg(STM32C0)]
131    spi1_rx_build!(impl Peripheral<P = impl TxDma<SPI1>> + 'static,impl Peripheral<P = impl RxDma<SPI1>> + 'static);
132    #[cfg(not(STM32C0))]
133    spi1_rx_build!(DMA1_CH3,DMA1_CH2);
134}
embassy_stm32_plus/builder/spi/spi1/rx.rs

embassy_stm32_plus/builder/spi/spi1/
rx.rs
