embassy_stm32_plus/builder/eth/
pins.rs

1use embassy_stm32::peripherals::{PA1, PA2, PA7, PB11, PB12, PB13, PC1, PC4, PC5};
2#[cfg(PD10)]
3use embassy_stm32::peripherals::PD10;
4#[cfg(PD8)]
5use embassy_stm32::peripherals::PD8;
6#[cfg(PD9)]
7use embassy_stm32::peripherals::PD9;
8
9/// eth crs pin
10pub enum EthCrs {
11    PA7(PA7),
12    #[cfg(PD8)]
13    PD8(PD8),
14}
15
16/// eth rx_d0 pin
17pub enum EthRxD0 {
18    PC4(PC4),
19    #[cfg(PD9)]
20    PD9(PD9),
21}
22
23/// eth rx_d1 pin
24pub enum EthRxD1 {
25    PC5(PC5),
26    #[cfg(PD10)]
27    PD10(PD10),
28}
29
30/// eth pin once
31pub(crate) struct EthPinOnce {
32    /// ref_clk pin
33    pub ref_clk: PA1,
34    /// mdio pin
35    pub mdio: PA2,
36    /// mdc pin
37    pub mdc: PC1,
38    /// tx_d0 pin
39    pub tx_d0: PB12,
40    /// tx_d1 pin
41    pub tx_d1: PB13,
42    /// tx_en pin
43    pub tx_en: PB11,
44}
45
46/// eth pins
47pub struct EthPins {
48    /// ref_clk pin
49    pub ref_clk: PA1,
50    /// mdio pin
51    pub mdio: PA2,
52    /// mdc pin
53    pub mdc: PC1,
54    /// crs pin
55    pub crs: EthCrs,
56    /// rx_d0 pin
57    pub rx_d0: EthRxD0,
58    /// rx_d1 pin
59    pub rx_d1: EthRxD1,
60    /// tx_d0 pin
61    pub tx_d0: PB12,
62    /// tx_d1 pin
63    pub tx_d1: PB13,
64    /// tx_en pin
65    pub tx_en: PB11,
66}
67
68/// custom method
69impl EthPins {
70    /// split pins
71    pub(crate) fn split(self) -> (EthCrs, EthRxD0, EthRxD1, EthPinOnce) {
72        (self.crs, self.rx_d0, self.rx_d1, EthPinOnce {
73            ref_clk: self.ref_clk,
74            mdio: self.mdio,
75            mdc: self.mdc,
76            tx_d0: self.tx_d0,
77            tx_d1: self.tx_d1,
78            tx_en: self.tx_en,
79        })
80    }
81}
embassy_stm32_plus/builder/eth/pins.rs

embassy_stm32_plus/builder/eth/
pins.rs
