embassy_net_wiznet/chip/
w5100s.rs

1use embedded_hal_async::spi::{Operation, SpiDevice};
2
3const SOCKET_BASE: u16 = 0x400;
4const TX_BASE: u16 = 0x4000;
5const RX_BASE: u16 = 0x6000;
6
7/// Wizard W5100S chip.
8pub enum W5100S {}
9
10impl super::Chip for W5100S {}
11impl super::SealedChip for W5100S {
12    type Address = u16;
13
14    const CHIP_VERSION: u8 = 0x51;
15
16    const COMMON_MODE: Self::Address = 0x00;
17    const COMMON_MAC: Self::Address = 0x09;
18    const COMMON_SOCKET_INTR: Self::Address = 0x16;
19    const COMMON_PHY_CFG: Self::Address = 0x3c;
20    const COMMON_VERSION: Self::Address = 0x80;
21
22    const SOCKET_MODE: Self::Address = SOCKET_BASE + 0x00;
23    const SOCKET_COMMAND: Self::Address = SOCKET_BASE + 0x01;
24    const SOCKET_RXBUF_SIZE: Self::Address = SOCKET_BASE + 0x1E;
25    const SOCKET_TXBUF_SIZE: Self::Address = SOCKET_BASE + 0x1F;
26    const SOCKET_TX_FREE_SIZE: Self::Address = SOCKET_BASE + 0x20;
27    const SOCKET_TX_DATA_WRITE_PTR: Self::Address = SOCKET_BASE + 0x24;
28    const SOCKET_RECVD_SIZE: Self::Address = SOCKET_BASE + 0x26;
29    const SOCKET_RX_DATA_READ_PTR: Self::Address = SOCKET_BASE + 0x28;
30    const SOCKET_INTR_MASK: Self::Address = SOCKET_BASE + 0x2C;
31    const SOCKET_INTR: Self::Address = SOCKET_BASE + 0x02;
32
33    const SOCKET_MODE_VALUE: u8 = (1 << 2) | (1 << 6);
34
35    const BUF_SIZE: u16 = 0x2000;
36    const AUTO_WRAP: bool = false;
37
38    fn rx_addr(addr: u16) -> Self::Address {
39        RX_BASE + addr
40    }
41
42    fn tx_addr(addr: u16) -> Self::Address {
43        TX_BASE + addr
44    }
45
46    async fn bus_read<SPI: SpiDevice>(
47        spi: &mut SPI,
48        address: Self::Address,
49        data: &mut [u8],
50    ) -> Result<(), SPI::Error> {
51        spi.transaction(&mut [
52            Operation::Write(&[0x0F, (address >> 8) as u8, address as u8]),
53            Operation::Read(data),
54        ])
55        .await
56    }
57
58    async fn bus_write<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &[u8]) -> Result<(), SPI::Error> {
59        spi.transaction(&mut [
60            Operation::Write(&[0xF0, (address >> 8) as u8, address as u8]),
61            Operation::Write(data),
62        ])
63        .await
64    }
65}
embassy_net_wiznet/chip/w5100s.rs

embassy_net_wiznet/chip/
w5100s.rs
