Struct efr32xg12p::prs::ch3_ctrl::_EDSELW

pub struct _EDSELW<'a> { /* fields omitted */ }

Proxy

Methods

impl<'a> _EDSELW<'a>

fn variant(self, variant: EDSELW) -> &'a mut W

Writes variant to the field

fn off(self) -> &'a mut W

Signal is left as it is

fn posedge(self) -> &'a mut W

A one HFCLK cycle pulse is generated for every positive edge of the incoming signal

fn negedge(self) -> &'a mut W

A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal

fn bothedges(self) -> &'a mut W

A one HFCLK clock cycle pulse is generated for every edge of the incoming signal

fn bits(self, value: u8) -> &'a mut W

Writes raw bits to the field