Struct efr32xg12p::adc0::ctrl::R
[−]
[src]
pub struct R { /* fields omitted */ }
Value read from the register
Methods
impl R
[src]
fn bits(&self) -> u32
[src]
Value of the register as raw bits
fn warmupmode(&self) -> WARMUPMODER
[src]
Bits 0:1 - Warm-up Mode
fn singledmawu(&self) -> SINGLEDMAWUR
[src]
Bit 2 - SINGLEFIFO DMA Wakeup
fn scandmawu(&self) -> SCANDMAWUR
[src]
Bit 3 - SCANFIFO DMA Wakeup
fn tailgate(&self) -> TAILGATER
[src]
Bit 4 - Conversion Tailgating
fn asyncclken(&self) -> ASYNCCLKENR
[src]
Bit 6 - Selects ASYNC CLK enable mode when ADCCLKMODE=1
fn adcclkmode(&self) -> ADCCLKMODER
[src]
Bit 7 - ADC Clock Mode
fn presc(&self) -> PRESCR
[src]
Bits 8:14 - Prescalar Setting for ADC Sample and Conversion clock
fn timebase(&self) -> TIMEBASER
[src]
Bits 16:22 - 1us Time Base
fn ovsrsel(&self) -> OVSRSELR
[src]
Bits 24:27 - Oversample Rate Select
fn dbghalt(&self) -> DBGHALTR
[src]
Bit 28 - Debug Mode Halt Enable
fn chconmode(&self) -> CHCONMODER
[src]
Bit 29 - Channel Connect
fn chconrefwarmidle(&self) -> CHCONREFWARMIDLER
[src]
Bits 30:31 - Channel Connect and Reference Warm Sel when ADC is IDLE