Struct efr32xg1::prs::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub swpulse: SWPULSE,
    pub swlevel: SWLEVEL,
    pub routepen: ROUTEPEN,
    pub routeloc0: ROUTELOC0,
    pub routeloc1: ROUTELOC1,
    pub routeloc2: ROUTELOC2,
    pub ctrl: CTRL,
    pub dmareq0: DMAREQ0,
    pub dmareq1: DMAREQ1,
    pub peek: PEEK,
    pub ch0_ctrl: CH0_CTRL,
    pub ch1_ctrl: CH1_CTRL,
    pub ch2_ctrl: CH2_CTRL,
    pub ch3_ctrl: CH3_CTRL,
    pub ch4_ctrl: CH4_CTRL,
    pub ch5_ctrl: CH5_CTRL,
    pub ch6_ctrl: CH6_CTRL,
    pub ch7_ctrl: CH7_CTRL,
    pub ch8_ctrl: CH8_CTRL,
    pub ch9_ctrl: CH9_CTRL,
    pub ch10_ctrl: CH10_CTRL,
    pub ch11_ctrl: CH11_CTRL,
    // some fields omitted
}

Register block

Fields

swpulse: SWPULSE

0x00 - Software Pulse Register

swlevel: SWLEVEL

0x04 - Software Level Register

routepen: ROUTEPEN

0x08 - I/O Routing Pin Enable Register

routeloc0: ROUTELOC0

0x10 - I/O Routing Location Register

routeloc1: ROUTELOC1

0x14 - I/O Routing Location Register

routeloc2: ROUTELOC2

0x18 - I/O Routing Location Register

ctrl: CTRL

0x20 - Control Register

dmareq0: DMAREQ0

0x24 - DMA Request 0 Register

dmareq1: DMAREQ1

0x28 - DMA Request 1 Register

peek: PEEK

0x30 - PRS Channel Values

ch0_ctrl: CH0_CTRL

0x40 - Channel Control Register

ch1_ctrl: CH1_CTRL

0x44 - Channel Control Register

ch2_ctrl: CH2_CTRL

0x48 - Channel Control Register

ch3_ctrl: CH3_CTRL

0x4c - Channel Control Register

ch4_ctrl: CH4_CTRL

0x50 - Channel Control Register

ch5_ctrl: CH5_CTRL

0x54 - Channel Control Register

ch6_ctrl: CH6_CTRL

0x58 - Channel Control Register

ch7_ctrl: CH7_CTRL

0x5c - Channel Control Register

ch8_ctrl: CH8_CTRL

0x60 - Channel Control Register

ch9_ctrl: CH9_CTRL

0x64 - Channel Control Register

ch10_ctrl: CH10_CTRL

0x68 - Channel Control Register

ch11_ctrl: CH11_CTRL

0x6c - Channel Control Register