[−][src]Struct efr32xg1::ldma::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub ctrl: CTRL,
    pub status: STATUS,
    pub sync: SYNC,
    pub chen: CHEN,
    pub chbusy: CHBUSY,
    pub chdone: CHDONE,
    pub dbghalt: DBGHALT,
    pub swreq: SWREQ,
    pub reqdis: REQDIS,
    pub reqpend: REQPEND,
    pub linkload: LINKLOAD,
    pub reqclear: REQCLEAR,
    pub if_: IF,
    pub ifs: IFS,
    pub ifc: IFC,
    pub ien: IEN,
    pub ch0_reqsel: CH0_REQSEL,
    pub ch0_cfg: CH0_CFG,
    pub ch0_loop: CH0_LOOP,
    pub ch0_ctrl: CH0_CTRL,
    pub ch0_src: CH0_SRC,
    pub ch0_dst: CH0_DST,
    pub ch0_link: CH0_LINK,
    pub ch1_reqsel: CH1_REQSEL,
    pub ch1_cfg: CH1_CFG,
    pub ch1_loop: CH1_LOOP,
    pub ch1_ctrl: CH1_CTRL,
    pub ch1_src: CH1_SRC,
    pub ch1_dst: CH1_DST,
    pub ch1_link: CH1_LINK,
    pub ch2_reqsel: CH2_REQSEL,
    pub ch2_cfg: CH2_CFG,
    pub ch2_loop: CH2_LOOP,
    pub ch2_ctrl: CH2_CTRL,
    pub ch2_src: CH2_SRC,
    pub ch2_dst: CH2_DST,
    pub ch2_link: CH2_LINK,
    pub ch3_reqsel: CH3_REQSEL,
    pub ch3_cfg: CH3_CFG,
    pub ch3_loop: CH3_LOOP,
    pub ch3_ctrl: CH3_CTRL,
    pub ch3_src: CH3_SRC,
    pub ch3_dst: CH3_DST,
    pub ch3_link: CH3_LINK,
    pub ch4_reqsel: CH4_REQSEL,
    pub ch4_cfg: CH4_CFG,
    pub ch4_loop: CH4_LOOP,
    pub ch4_ctrl: CH4_CTRL,
    pub ch4_src: CH4_SRC,
    pub ch4_dst: CH4_DST,
    pub ch4_link: CH4_LINK,
    pub ch5_reqsel: CH5_REQSEL,
    pub ch5_cfg: CH5_CFG,
    pub ch5_loop: CH5_LOOP,
    pub ch5_ctrl: CH5_CTRL,
    pub ch5_src: CH5_SRC,
    pub ch5_dst: CH5_DST,
    pub ch5_link: CH5_LINK,
    pub ch6_reqsel: CH6_REQSEL,
    pub ch6_cfg: CH6_CFG,
    pub ch6_loop: CH6_LOOP,
    pub ch6_ctrl: CH6_CTRL,
    pub ch6_src: CH6_SRC,
    pub ch6_dst: CH6_DST,
    pub ch6_link: CH6_LINK,
    pub ch7_reqsel: CH7_REQSEL,
    pub ch7_cfg: CH7_CFG,
    pub ch7_loop: CH7_LOOP,
    pub ch7_ctrl: CH7_CTRL,
    pub ch7_src: CH7_SRC,
    pub ch7_dst: CH7_DST,
    pub ch7_link: CH7_LINK,
    // some fields omitted
}

Register block

Fields

ctrl: CTRL

0x00 - DMA Control Register

status: STATUS

0x04 - DMA Status Register

sync: SYNC

0x08 - DMA Synchronization Trigger Register (Single-Cycle RMW)

chen: CHEN

0x20 - DMA Channel Enable Register (Single-Cycle RMW)

chbusy: CHBUSY

0x24 - DMA Channel Busy Register

chdone: CHDONE

0x28 - DMA Channel Linking Done Register (Single-Cycle RMW)

dbghalt: DBGHALT

0x2c - DMA Channel Debug Halt Register

swreq: SWREQ

0x30 - DMA Channel Software Transfer Request Register

reqdis: REQDIS

0x34 - DMA Channel Request Disable Register

reqpend: REQPEND

0x38 - DMA Channel Requests Pending Register

linkload: LINKLOAD

0x3c - DMA Channel Link Load Register

reqclear: REQCLEAR

0x40 - DMA Channel Request Clear Register

if_: IF

0x60 - Interrupt Flag Register

ifs: IFS

0x64 - Interrupt Flag Set Register

ifc: IFC

0x68 - Interrupt Flag Clear Register

ien: IEN

0x6c - Interrupt Enable Register

ch0_reqsel: CH0_REQSEL

0x80 - Channel Peripheral Request Select Register

ch0_cfg: CH0_CFG

0x84 - Channel Configuration Register

ch0_loop: CH0_LOOP

0x88 - Channel Loop Counter Register

ch0_ctrl: CH0_CTRL

0x8c - Channel Descriptor Control Word Register

ch0_src: CH0_SRC

0x90 - Channel Descriptor Source Data Address Register

ch0_dst: CH0_DST

0x94 - Channel Descriptor Destination Data Address Register

ch0_link: CH0_LINK

0x98 - Channel Descriptor Link Structure Address Register

ch1_reqsel: CH1_REQSEL

0xb0 - Channel Peripheral Request Select Register

ch1_cfg: CH1_CFG

0xb4 - Channel Configuration Register

ch1_loop: CH1_LOOP

0xb8 - Channel Loop Counter Register

ch1_ctrl: CH1_CTRL

0xbc - Channel Descriptor Control Word Register

ch1_src: CH1_SRC

0xc0 - Channel Descriptor Source Data Address Register

ch1_dst: CH1_DST

0xc4 - Channel Descriptor Destination Data Address Register

ch1_link: CH1_LINK

0xc8 - Channel Descriptor Link Structure Address Register

ch2_reqsel: CH2_REQSEL

0xe0 - Channel Peripheral Request Select Register

ch2_cfg: CH2_CFG

0xe4 - Channel Configuration Register

ch2_loop: CH2_LOOP

0xe8 - Channel Loop Counter Register

ch2_ctrl: CH2_CTRL

0xec - Channel Descriptor Control Word Register

ch2_src: CH2_SRC

0xf0 - Channel Descriptor Source Data Address Register

ch2_dst: CH2_DST

0xf4 - Channel Descriptor Destination Data Address Register

ch2_link: CH2_LINK

0xf8 - Channel Descriptor Link Structure Address Register

ch3_reqsel: CH3_REQSEL

0x110 - Channel Peripheral Request Select Register

ch3_cfg: CH3_CFG

0x114 - Channel Configuration Register

ch3_loop: CH3_LOOP

0x118 - Channel Loop Counter Register

ch3_ctrl: CH3_CTRL

0x11c - Channel Descriptor Control Word Register

ch3_src: CH3_SRC

0x120 - Channel Descriptor Source Data Address Register

ch3_dst: CH3_DST

0x124 - Channel Descriptor Destination Data Address Register

ch3_link: CH3_LINK

0x128 - Channel Descriptor Link Structure Address Register

ch4_reqsel: CH4_REQSEL

0x140 - Channel Peripheral Request Select Register

ch4_cfg: CH4_CFG

0x144 - Channel Configuration Register

ch4_loop: CH4_LOOP

0x148 - Channel Loop Counter Register

ch4_ctrl: CH4_CTRL

0x14c - Channel Descriptor Control Word Register

ch4_src: CH4_SRC

0x150 - Channel Descriptor Source Data Address Register

ch4_dst: CH4_DST

0x154 - Channel Descriptor Destination Data Address Register

ch4_link: CH4_LINK

0x158 - Channel Descriptor Link Structure Address Register

ch5_reqsel: CH5_REQSEL

0x170 - Channel Peripheral Request Select Register

ch5_cfg: CH5_CFG

0x174 - Channel Configuration Register

ch5_loop: CH5_LOOP

0x178 - Channel Loop Counter Register

ch5_ctrl: CH5_CTRL

0x17c - Channel Descriptor Control Word Register

ch5_src: CH5_SRC

0x180 - Channel Descriptor Source Data Address Register

ch5_dst: CH5_DST

0x184 - Channel Descriptor Destination Data Address Register

ch5_link: CH5_LINK

0x188 - Channel Descriptor Link Structure Address Register

ch6_reqsel: CH6_REQSEL

0x1a0 - Channel Peripheral Request Select Register

ch6_cfg: CH6_CFG

0x1a4 - Channel Configuration Register

ch6_loop: CH6_LOOP

0x1a8 - Channel Loop Counter Register

ch6_ctrl: CH6_CTRL

0x1ac - Channel Descriptor Control Word Register

ch6_src: CH6_SRC

0x1b0 - Channel Descriptor Source Data Address Register

ch6_dst: CH6_DST

0x1b4 - Channel Descriptor Destination Data Address Register

ch6_link: CH6_LINK

0x1b8 - Channel Descriptor Link Structure Address Register

ch7_reqsel: CH7_REQSEL

0x1d0 - Channel Peripheral Request Select Register

ch7_cfg: CH7_CFG

0x1d4 - Channel Configuration Register

ch7_loop: CH7_LOOP

0x1d8 - Channel Loop Counter Register

ch7_ctrl: CH7_CTRL

0x1dc - Channel Descriptor Control Word Register

ch7_src: CH7_SRC

0x1e0 - Channel Descriptor Source Data Address Register

ch7_dst: CH7_DST

0x1e4 - Channel Descriptor Destination Data Address Register

ch7_link: CH7_LINK

0x1e8 - Channel Descriptor Link Structure Address Register

Auto Trait Implementations

`impl Send for RegisterBlock`

`impl !Sync for RegisterBlock`

Blanket Implementations

`impl<T, U> TryFrom for T where T: From<U>,`
[src]

`type Error = !`

🔬 This is a nightly-only experimental API. (try_from)

The type returned in the event of a conversion error.

`impl<T> From for T`
[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,`
[src]

`type Error = <U as TryFrom<T>>::Error`

🔬 This is a nightly-only experimental API. (try_from)

The type returned in the event of a conversion error.

[−][src]Struct efr32xg1::ldma::RegisterBlock

Fields

Auto Trait Implementations

`impl Send for RegisterBlock`

`impl !Sync for RegisterBlock`

Blanket Implementations

`impl<T, U> TryFrom for T where T: From<U>,`
[src]

`type Error = !`

`fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>`
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`impl<T> From for T`
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`fn from(t: T) -> T`
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`impl<T, U> TryInto for T where U: TryFrom<T>,`
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`type Error = <U as TryFrom<T>>::Error`

`fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>`
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`impl<T, U> Into for T where U: From<T>,`
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`fn into(self) -> U`
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`impl<T> Borrow for T where T: ?Sized,`
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`fn borrow(&self) -> &T`
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`impl<T> BorrowMut for T where T: ?Sized,`
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`fn borrow_mut(&mut self) -> &mut T`
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`impl<T> Any for T where T: 'static + ?Sized,`
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`fn get_type_id(&self) -> TypeId`
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[−][src]Struct efr32xg1::ldma::RegisterBlock

Fields

Auto Trait Implementations

impl Send for RegisterBlock

impl !Sync for RegisterBlock

Blanket Implementations

impl<T, U> TryFrom for T where T: From<U>, [src]

type Error = !

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>[src]

impl<T> From for T[src]

fn from(t: T) -> T[src]

impl<T, U> TryInto for T where U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>[src]

impl<T, U> Into for T where U: From<T>, [src]

fn into(self) -> U[src]

impl<T> Borrow for T where T: ?Sized, [src]

fn borrow(&self) -> &T[src]

impl<T> BorrowMut for T where T: ?Sized, [src]

fn borrow_mut(&mut self) -> &mut T[src]

impl<T> Any for T where T: 'static + ?Sized, [src]

fn get_type_id(&self) -> TypeId[src]

`impl Send for RegisterBlock`

`impl !Sync for RegisterBlock`

`impl<T, U> TryFrom for T where T: From<U>,`
[src]

`type Error = !`

`fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>`
[src]

`impl<T> From for T`
[src]

`fn from(t: T) -> T`
[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,`
[src]

`type Error = <U as TryFrom<T>>::Error`

`fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>`
[src]

`impl<T, U> Into for T where U: From<T>,`
[src]

`fn into(self) -> U`
[src]

`impl<T> Borrow for T where T: ?Sized,`
[src]

`fn borrow(&self) -> &T`
[src]

`impl<T> BorrowMut for T where T: ?Sized,`
[src]

`fn borrow_mut(&mut self) -> &mut T`
[src]

`impl<T> Any for T where T: 'static + ?Sized,`
[src]

`fn get_type_id(&self) -> TypeId`
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