efm32zg210_pac/dma/
chreqmaskc.rs

1#[doc = "Register `CHREQMASKC` writer"]
2pub struct W(crate::W<CHREQMASKC_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CHREQMASKC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CHREQMASKC_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CHREQMASKC_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `CH0REQMASKC` writer - Channel 0 Request Mask Clear"]
23pub type CH0REQMASKC_W<'a> = crate::BitWriter<'a, u32, CHREQMASKC_SPEC, bool, 0>;
24#[doc = "Field `CH1REQMASKC` writer - Channel 1 Request Mask Clear"]
25pub type CH1REQMASKC_W<'a> = crate::BitWriter<'a, u32, CHREQMASKC_SPEC, bool, 1>;
26#[doc = "Field `CH2REQMASKC` writer - Channel 2 Request Mask Clear"]
27pub type CH2REQMASKC_W<'a> = crate::BitWriter<'a, u32, CHREQMASKC_SPEC, bool, 2>;
28#[doc = "Field `CH3REQMASKC` writer - Channel 3 Request Mask Clear"]
29pub type CH3REQMASKC_W<'a> = crate::BitWriter<'a, u32, CHREQMASKC_SPEC, bool, 3>;
30impl W {
31    #[doc = "Bit 0 - Channel 0 Request Mask Clear"]
32    #[inline(always)]
33    pub fn ch0reqmaskc(&mut self) -> CH0REQMASKC_W {
34        CH0REQMASKC_W::new(self)
35    }
36    #[doc = "Bit 1 - Channel 1 Request Mask Clear"]
37    #[inline(always)]
38    pub fn ch1reqmaskc(&mut self) -> CH1REQMASKC_W {
39        CH1REQMASKC_W::new(self)
40    }
41    #[doc = "Bit 2 - Channel 2 Request Mask Clear"]
42    #[inline(always)]
43    pub fn ch2reqmaskc(&mut self) -> CH2REQMASKC_W {
44        CH2REQMASKC_W::new(self)
45    }
46    #[doc = "Bit 3 - Channel 3 Request Mask Clear"]
47    #[inline(always)]
48    pub fn ch3reqmaskc(&mut self) -> CH3REQMASKC_W {
49        CH3REQMASKC_W::new(self)
50    }
51    #[doc = "Writes raw bits to the register."]
52    #[inline(always)]
53    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
54        self.0.bits(bits);
55        self
56    }
57}
58#[doc = "Channel Request Mask Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chreqmaskc](index.html) module"]
59pub struct CHREQMASKC_SPEC;
60impl crate::RegisterSpec for CHREQMASKC_SPEC {
61    type Ux = u32;
62}
63#[doc = "`write(|w| ..)` method takes [chreqmaskc::W](W) writer structure"]
64impl crate::Writable for CHREQMASKC_SPEC {
65    type Writer = W;
66}
67#[doc = "`reset()` method sets CHREQMASKC to value 0"]
68impl crate::Resettable for CHREQMASKC_SPEC {
69    #[inline(always)]
70    fn reset_value() -> Self::Ux {
71        0
72    }
73}
efm32zg210_pac/dma/chreqmaskc.rs

efm32zg210_pac/dma/
chreqmaskc.rs
