efm32zg110_pac/prs/
ch1_ctrl.rs

1#[doc = "Register `CH1_CTRL` reader"]
2pub struct R(crate::R<CH1_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH1_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH1_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH1_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH1_CTRL` writer"]
17pub struct W(crate::W<CH1_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH1_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH1_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH1_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH1_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Voltage Comparator"]
48    VCMP = 1,
49    #[doc = "2: Analog Comparator 0"]
50    ACMP0 = 2,
51    #[doc = "8: Analog to Digital Converter 0"]
52    ADC0 = 8,
53    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
54    USART1 = 17,
55    #[doc = "28: Timer 0"]
56    TIMER0 = 28,
57    #[doc = "29: Timer 1"]
58    TIMER1 = 29,
59    #[doc = "40: Real-Time Counter"]
60    RTC = 40,
61    #[doc = "48: General purpose Input/Output"]
62    GPIOL = 48,
63    #[doc = "49: General purpose Input/Output"]
64    GPIOH = 49,
65    #[doc = "54: Pulse Counter 0"]
66    PCNT0 = 54,
67}
68impl From<SOURCESEL_A> for u8 {
69    #[inline(always)]
70    fn from(variant: SOURCESEL_A) -> Self {
71        variant as _
72    }
73}
74#[doc = "Field `SOURCESEL` reader - Source Select"]
75pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
76impl SOURCESEL_R {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub fn variant(&self) -> Option<SOURCESEL_A> {
80        match self.bits {
81            0 => Some(SOURCESEL_A::NONE),
82            1 => Some(SOURCESEL_A::VCMP),
83            2 => Some(SOURCESEL_A::ACMP0),
84            8 => Some(SOURCESEL_A::ADC0),
85            17 => Some(SOURCESEL_A::USART1),
86            28 => Some(SOURCESEL_A::TIMER0),
87            29 => Some(SOURCESEL_A::TIMER1),
88            40 => Some(SOURCESEL_A::RTC),
89            48 => Some(SOURCESEL_A::GPIOL),
90            49 => Some(SOURCESEL_A::GPIOH),
91            54 => Some(SOURCESEL_A::PCNT0),
92            _ => None,
93        }
94    }
95    #[doc = "Checks if the value of the field is `NONE`"]
96    #[inline(always)]
97    pub fn is_none(&self) -> bool {
98        *self == SOURCESEL_A::NONE
99    }
100    #[doc = "Checks if the value of the field is `VCMP`"]
101    #[inline(always)]
102    pub fn is_vcmp(&self) -> bool {
103        *self == SOURCESEL_A::VCMP
104    }
105    #[doc = "Checks if the value of the field is `ACMP0`"]
106    #[inline(always)]
107    pub fn is_acmp0(&self) -> bool {
108        *self == SOURCESEL_A::ACMP0
109    }
110    #[doc = "Checks if the value of the field is `ADC0`"]
111    #[inline(always)]
112    pub fn is_adc0(&self) -> bool {
113        *self == SOURCESEL_A::ADC0
114    }
115    #[doc = "Checks if the value of the field is `USART1`"]
116    #[inline(always)]
117    pub fn is_usart1(&self) -> bool {
118        *self == SOURCESEL_A::USART1
119    }
120    #[doc = "Checks if the value of the field is `TIMER0`"]
121    #[inline(always)]
122    pub fn is_timer0(&self) -> bool {
123        *self == SOURCESEL_A::TIMER0
124    }
125    #[doc = "Checks if the value of the field is `TIMER1`"]
126    #[inline(always)]
127    pub fn is_timer1(&self) -> bool {
128        *self == SOURCESEL_A::TIMER1
129    }
130    #[doc = "Checks if the value of the field is `RTC`"]
131    #[inline(always)]
132    pub fn is_rtc(&self) -> bool {
133        *self == SOURCESEL_A::RTC
134    }
135    #[doc = "Checks if the value of the field is `GPIOL`"]
136    #[inline(always)]
137    pub fn is_gpiol(&self) -> bool {
138        *self == SOURCESEL_A::GPIOL
139    }
140    #[doc = "Checks if the value of the field is `GPIOH`"]
141    #[inline(always)]
142    pub fn is_gpioh(&self) -> bool {
143        *self == SOURCESEL_A::GPIOH
144    }
145    #[doc = "Checks if the value of the field is `PCNT0`"]
146    #[inline(always)]
147    pub fn is_pcnt0(&self) -> bool {
148        *self == SOURCESEL_A::PCNT0
149    }
150}
151#[doc = "Field `SOURCESEL` writer - Source Select"]
152pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH1_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
153impl<'a> SOURCESEL_W<'a> {
154    #[doc = "No source selected"]
155    #[inline(always)]
156    pub fn none(self) -> &'a mut W {
157        self.variant(SOURCESEL_A::NONE)
158    }
159    #[doc = "Voltage Comparator"]
160    #[inline(always)]
161    pub fn vcmp(self) -> &'a mut W {
162        self.variant(SOURCESEL_A::VCMP)
163    }
164    #[doc = "Analog Comparator 0"]
165    #[inline(always)]
166    pub fn acmp0(self) -> &'a mut W {
167        self.variant(SOURCESEL_A::ACMP0)
168    }
169    #[doc = "Analog to Digital Converter 0"]
170    #[inline(always)]
171    pub fn adc0(self) -> &'a mut W {
172        self.variant(SOURCESEL_A::ADC0)
173    }
174    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
175    #[inline(always)]
176    pub fn usart1(self) -> &'a mut W {
177        self.variant(SOURCESEL_A::USART1)
178    }
179    #[doc = "Timer 0"]
180    #[inline(always)]
181    pub fn timer0(self) -> &'a mut W {
182        self.variant(SOURCESEL_A::TIMER0)
183    }
184    #[doc = "Timer 1"]
185    #[inline(always)]
186    pub fn timer1(self) -> &'a mut W {
187        self.variant(SOURCESEL_A::TIMER1)
188    }
189    #[doc = "Real-Time Counter"]
190    #[inline(always)]
191    pub fn rtc(self) -> &'a mut W {
192        self.variant(SOURCESEL_A::RTC)
193    }
194    #[doc = "General purpose Input/Output"]
195    #[inline(always)]
196    pub fn gpiol(self) -> &'a mut W {
197        self.variant(SOURCESEL_A::GPIOL)
198    }
199    #[doc = "General purpose Input/Output"]
200    #[inline(always)]
201    pub fn gpioh(self) -> &'a mut W {
202        self.variant(SOURCESEL_A::GPIOH)
203    }
204    #[doc = "Pulse Counter 0"]
205    #[inline(always)]
206    pub fn pcnt0(self) -> &'a mut W {
207        self.variant(SOURCESEL_A::PCNT0)
208    }
209}
210#[doc = "Edge Detect Select\n\nValue on reset: 0"]
211#[derive(Clone, Copy, Debug, PartialEq)]
212#[repr(u8)]
213pub enum EDSEL_A {
214    #[doc = "0: Signal is left as it is"]
215    OFF = 0,
216    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
217    POSEDGE = 1,
218    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
219    NEGEDGE = 2,
220    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
221    BOTHEDGES = 3,
222}
223impl From<EDSEL_A> for u8 {
224    #[inline(always)]
225    fn from(variant: EDSEL_A) -> Self {
226        variant as _
227    }
228}
229#[doc = "Field `EDSEL` reader - Edge Detect Select"]
230pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
231impl EDSEL_R {
232    #[doc = "Get enumerated values variant"]
233    #[inline(always)]
234    pub fn variant(&self) -> EDSEL_A {
235        match self.bits {
236            0 => EDSEL_A::OFF,
237            1 => EDSEL_A::POSEDGE,
238            2 => EDSEL_A::NEGEDGE,
239            3 => EDSEL_A::BOTHEDGES,
240            _ => unreachable!(),
241        }
242    }
243    #[doc = "Checks if the value of the field is `OFF`"]
244    #[inline(always)]
245    pub fn is_off(&self) -> bool {
246        *self == EDSEL_A::OFF
247    }
248    #[doc = "Checks if the value of the field is `POSEDGE`"]
249    #[inline(always)]
250    pub fn is_posedge(&self) -> bool {
251        *self == EDSEL_A::POSEDGE
252    }
253    #[doc = "Checks if the value of the field is `NEGEDGE`"]
254    #[inline(always)]
255    pub fn is_negedge(&self) -> bool {
256        *self == EDSEL_A::NEGEDGE
257    }
258    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
259    #[inline(always)]
260    pub fn is_bothedges(&self) -> bool {
261        *self == EDSEL_A::BOTHEDGES
262    }
263}
264#[doc = "Field `EDSEL` writer - Edge Detect Select"]
265pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH1_CTRL_SPEC, u8, EDSEL_A, 2, 24>;
266impl<'a> EDSEL_W<'a> {
267    #[doc = "Signal is left as it is"]
268    #[inline(always)]
269    pub fn off(self) -> &'a mut W {
270        self.variant(EDSEL_A::OFF)
271    }
272    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
273    #[inline(always)]
274    pub fn posedge(self) -> &'a mut W {
275        self.variant(EDSEL_A::POSEDGE)
276    }
277    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
278    #[inline(always)]
279    pub fn negedge(self) -> &'a mut W {
280        self.variant(EDSEL_A::NEGEDGE)
281    }
282    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
283    #[inline(always)]
284    pub fn bothedges(self) -> &'a mut W {
285        self.variant(EDSEL_A::BOTHEDGES)
286    }
287}
288#[doc = "Field `ASYNC` reader - Asynchronous reflex"]
289pub type ASYNC_R = crate::BitReader<bool>;
290#[doc = "Field `ASYNC` writer - Asynchronous reflex"]
291pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH1_CTRL_SPEC, bool, 28>;
292impl R {
293    #[doc = "Bits 0:2 - Signal Select"]
294    #[inline(always)]
295    pub fn sigsel(&self) -> SIGSEL_R {
296        SIGSEL_R::new((self.bits & 7) as u8)
297    }
298    #[doc = "Bits 16:21 - Source Select"]
299    #[inline(always)]
300    pub fn sourcesel(&self) -> SOURCESEL_R {
301        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
302    }
303    #[doc = "Bits 24:25 - Edge Detect Select"]
304    #[inline(always)]
305    pub fn edsel(&self) -> EDSEL_R {
306        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
307    }
308    #[doc = "Bit 28 - Asynchronous reflex"]
309    #[inline(always)]
310    pub fn async_(&self) -> ASYNC_R {
311        ASYNC_R::new(((self.bits >> 28) & 1) != 0)
312    }
313}
314impl W {
315    #[doc = "Bits 0:2 - Signal Select"]
316    #[inline(always)]
317    pub fn sigsel(&mut self) -> SIGSEL_W {
318        SIGSEL_W::new(self)
319    }
320    #[doc = "Bits 16:21 - Source Select"]
321    #[inline(always)]
322    pub fn sourcesel(&mut self) -> SOURCESEL_W {
323        SOURCESEL_W::new(self)
324    }
325    #[doc = "Bits 24:25 - Edge Detect Select"]
326    #[inline(always)]
327    pub fn edsel(&mut self) -> EDSEL_W {
328        EDSEL_W::new(self)
329    }
330    #[doc = "Bit 28 - Asynchronous reflex"]
331    #[inline(always)]
332    pub fn async_(&mut self) -> ASYNC_W {
333        ASYNC_W::new(self)
334    }
335    #[doc = "Writes raw bits to the register."]
336    #[inline(always)]
337    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
338        self.0.bits(bits);
339        self
340    }
341}
342#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch1_ctrl](index.html) module"]
343pub struct CH1_CTRL_SPEC;
344impl crate::RegisterSpec for CH1_CTRL_SPEC {
345    type Ux = u32;
346}
347#[doc = "`read()` method returns [ch1_ctrl::R](R) reader structure"]
348impl crate::Readable for CH1_CTRL_SPEC {
349    type Reader = R;
350}
351#[doc = "`write(|w| ..)` method takes [ch1_ctrl::W](W) writer structure"]
352impl crate::Writable for CH1_CTRL_SPEC {
353    type Writer = W;
354}
355#[doc = "`reset()` method sets CH1_CTRL to value 0"]
356impl crate::Resettable for CH1_CTRL_SPEC {
357    #[inline(always)]
358    fn reset_value() -> Self::Ux {
359        0
360    }
361}
efm32zg110_pac/prs/ch1_ctrl.rs

efm32zg110_pac/prs/
ch1_ctrl.rs
