efm32zg108_pac/prs/
ch0_ctrl.rs

1#[doc = "Register `CH0_CTRL` reader"]
2pub struct R(crate::R<CH0_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH0_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH0_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH0_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH0_CTRL` writer"]
17pub struct W(crate::W<CH0_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH0_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH0_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH0_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH0_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Voltage Comparator"]
48    VCMP = 1,
49    #[doc = "2: Analog Comparator 0"]
50    ACMP0 = 2,
51    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
52    USART1 = 17,
53    #[doc = "28: Timer 0"]
54    TIMER0 = 28,
55    #[doc = "29: Timer 1"]
56    TIMER1 = 29,
57    #[doc = "40: Real-Time Counter"]
58    RTC = 40,
59    #[doc = "48: General purpose Input/Output"]
60    GPIOL = 48,
61    #[doc = "49: General purpose Input/Output"]
62    GPIOH = 49,
63    #[doc = "54: Pulse Counter 0"]
64    PCNT0 = 54,
65}
66impl From<SOURCESEL_A> for u8 {
67    #[inline(always)]
68    fn from(variant: SOURCESEL_A) -> Self {
69        variant as _
70    }
71}
72#[doc = "Field `SOURCESEL` reader - Source Select"]
73pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
74impl SOURCESEL_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub fn variant(&self) -> Option<SOURCESEL_A> {
78        match self.bits {
79            0 => Some(SOURCESEL_A::NONE),
80            1 => Some(SOURCESEL_A::VCMP),
81            2 => Some(SOURCESEL_A::ACMP0),
82            17 => Some(SOURCESEL_A::USART1),
83            28 => Some(SOURCESEL_A::TIMER0),
84            29 => Some(SOURCESEL_A::TIMER1),
85            40 => Some(SOURCESEL_A::RTC),
86            48 => Some(SOURCESEL_A::GPIOL),
87            49 => Some(SOURCESEL_A::GPIOH),
88            54 => Some(SOURCESEL_A::PCNT0),
89            _ => None,
90        }
91    }
92    #[doc = "Checks if the value of the field is `NONE`"]
93    #[inline(always)]
94    pub fn is_none(&self) -> bool {
95        *self == SOURCESEL_A::NONE
96    }
97    #[doc = "Checks if the value of the field is `VCMP`"]
98    #[inline(always)]
99    pub fn is_vcmp(&self) -> bool {
100        *self == SOURCESEL_A::VCMP
101    }
102    #[doc = "Checks if the value of the field is `ACMP0`"]
103    #[inline(always)]
104    pub fn is_acmp0(&self) -> bool {
105        *self == SOURCESEL_A::ACMP0
106    }
107    #[doc = "Checks if the value of the field is `USART1`"]
108    #[inline(always)]
109    pub fn is_usart1(&self) -> bool {
110        *self == SOURCESEL_A::USART1
111    }
112    #[doc = "Checks if the value of the field is `TIMER0`"]
113    #[inline(always)]
114    pub fn is_timer0(&self) -> bool {
115        *self == SOURCESEL_A::TIMER0
116    }
117    #[doc = "Checks if the value of the field is `TIMER1`"]
118    #[inline(always)]
119    pub fn is_timer1(&self) -> bool {
120        *self == SOURCESEL_A::TIMER1
121    }
122    #[doc = "Checks if the value of the field is `RTC`"]
123    #[inline(always)]
124    pub fn is_rtc(&self) -> bool {
125        *self == SOURCESEL_A::RTC
126    }
127    #[doc = "Checks if the value of the field is `GPIOL`"]
128    #[inline(always)]
129    pub fn is_gpiol(&self) -> bool {
130        *self == SOURCESEL_A::GPIOL
131    }
132    #[doc = "Checks if the value of the field is `GPIOH`"]
133    #[inline(always)]
134    pub fn is_gpioh(&self) -> bool {
135        *self == SOURCESEL_A::GPIOH
136    }
137    #[doc = "Checks if the value of the field is `PCNT0`"]
138    #[inline(always)]
139    pub fn is_pcnt0(&self) -> bool {
140        *self == SOURCESEL_A::PCNT0
141    }
142}
143#[doc = "Field `SOURCESEL` writer - Source Select"]
144pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH0_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
145impl<'a> SOURCESEL_W<'a> {
146    #[doc = "No source selected"]
147    #[inline(always)]
148    pub fn none(self) -> &'a mut W {
149        self.variant(SOURCESEL_A::NONE)
150    }
151    #[doc = "Voltage Comparator"]
152    #[inline(always)]
153    pub fn vcmp(self) -> &'a mut W {
154        self.variant(SOURCESEL_A::VCMP)
155    }
156    #[doc = "Analog Comparator 0"]
157    #[inline(always)]
158    pub fn acmp0(self) -> &'a mut W {
159        self.variant(SOURCESEL_A::ACMP0)
160    }
161    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
162    #[inline(always)]
163    pub fn usart1(self) -> &'a mut W {
164        self.variant(SOURCESEL_A::USART1)
165    }
166    #[doc = "Timer 0"]
167    #[inline(always)]
168    pub fn timer0(self) -> &'a mut W {
169        self.variant(SOURCESEL_A::TIMER0)
170    }
171    #[doc = "Timer 1"]
172    #[inline(always)]
173    pub fn timer1(self) -> &'a mut W {
174        self.variant(SOURCESEL_A::TIMER1)
175    }
176    #[doc = "Real-Time Counter"]
177    #[inline(always)]
178    pub fn rtc(self) -> &'a mut W {
179        self.variant(SOURCESEL_A::RTC)
180    }
181    #[doc = "General purpose Input/Output"]
182    #[inline(always)]
183    pub fn gpiol(self) -> &'a mut W {
184        self.variant(SOURCESEL_A::GPIOL)
185    }
186    #[doc = "General purpose Input/Output"]
187    #[inline(always)]
188    pub fn gpioh(self) -> &'a mut W {
189        self.variant(SOURCESEL_A::GPIOH)
190    }
191    #[doc = "Pulse Counter 0"]
192    #[inline(always)]
193    pub fn pcnt0(self) -> &'a mut W {
194        self.variant(SOURCESEL_A::PCNT0)
195    }
196}
197#[doc = "Edge Detect Select\n\nValue on reset: 0"]
198#[derive(Clone, Copy, Debug, PartialEq)]
199#[repr(u8)]
200pub enum EDSEL_A {
201    #[doc = "0: Signal is left as it is"]
202    OFF = 0,
203    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
204    POSEDGE = 1,
205    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
206    NEGEDGE = 2,
207    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
208    BOTHEDGES = 3,
209}
210impl From<EDSEL_A> for u8 {
211    #[inline(always)]
212    fn from(variant: EDSEL_A) -> Self {
213        variant as _
214    }
215}
216#[doc = "Field `EDSEL` reader - Edge Detect Select"]
217pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
218impl EDSEL_R {
219    #[doc = "Get enumerated values variant"]
220    #[inline(always)]
221    pub fn variant(&self) -> EDSEL_A {
222        match self.bits {
223            0 => EDSEL_A::OFF,
224            1 => EDSEL_A::POSEDGE,
225            2 => EDSEL_A::NEGEDGE,
226            3 => EDSEL_A::BOTHEDGES,
227            _ => unreachable!(),
228        }
229    }
230    #[doc = "Checks if the value of the field is `OFF`"]
231    #[inline(always)]
232    pub fn is_off(&self) -> bool {
233        *self == EDSEL_A::OFF
234    }
235    #[doc = "Checks if the value of the field is `POSEDGE`"]
236    #[inline(always)]
237    pub fn is_posedge(&self) -> bool {
238        *self == EDSEL_A::POSEDGE
239    }
240    #[doc = "Checks if the value of the field is `NEGEDGE`"]
241    #[inline(always)]
242    pub fn is_negedge(&self) -> bool {
243        *self == EDSEL_A::NEGEDGE
244    }
245    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
246    #[inline(always)]
247    pub fn is_bothedges(&self) -> bool {
248        *self == EDSEL_A::BOTHEDGES
249    }
250}
251#[doc = "Field `EDSEL` writer - Edge Detect Select"]
252pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH0_CTRL_SPEC, u8, EDSEL_A, 2, 24>;
253impl<'a> EDSEL_W<'a> {
254    #[doc = "Signal is left as it is"]
255    #[inline(always)]
256    pub fn off(self) -> &'a mut W {
257        self.variant(EDSEL_A::OFF)
258    }
259    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
260    #[inline(always)]
261    pub fn posedge(self) -> &'a mut W {
262        self.variant(EDSEL_A::POSEDGE)
263    }
264    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
265    #[inline(always)]
266    pub fn negedge(self) -> &'a mut W {
267        self.variant(EDSEL_A::NEGEDGE)
268    }
269    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
270    #[inline(always)]
271    pub fn bothedges(self) -> &'a mut W {
272        self.variant(EDSEL_A::BOTHEDGES)
273    }
274}
275#[doc = "Field `ASYNC` reader - Asynchronous reflex"]
276pub type ASYNC_R = crate::BitReader<bool>;
277#[doc = "Field `ASYNC` writer - Asynchronous reflex"]
278pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH0_CTRL_SPEC, bool, 28>;
279impl R {
280    #[doc = "Bits 0:2 - Signal Select"]
281    #[inline(always)]
282    pub fn sigsel(&self) -> SIGSEL_R {
283        SIGSEL_R::new((self.bits & 7) as u8)
284    }
285    #[doc = "Bits 16:21 - Source Select"]
286    #[inline(always)]
287    pub fn sourcesel(&self) -> SOURCESEL_R {
288        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
289    }
290    #[doc = "Bits 24:25 - Edge Detect Select"]
291    #[inline(always)]
292    pub fn edsel(&self) -> EDSEL_R {
293        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
294    }
295    #[doc = "Bit 28 - Asynchronous reflex"]
296    #[inline(always)]
297    pub fn async_(&self) -> ASYNC_R {
298        ASYNC_R::new(((self.bits >> 28) & 1) != 0)
299    }
300}
301impl W {
302    #[doc = "Bits 0:2 - Signal Select"]
303    #[inline(always)]
304    pub fn sigsel(&mut self) -> SIGSEL_W {
305        SIGSEL_W::new(self)
306    }
307    #[doc = "Bits 16:21 - Source Select"]
308    #[inline(always)]
309    pub fn sourcesel(&mut self) -> SOURCESEL_W {
310        SOURCESEL_W::new(self)
311    }
312    #[doc = "Bits 24:25 - Edge Detect Select"]
313    #[inline(always)]
314    pub fn edsel(&mut self) -> EDSEL_W {
315        EDSEL_W::new(self)
316    }
317    #[doc = "Bit 28 - Asynchronous reflex"]
318    #[inline(always)]
319    pub fn async_(&mut self) -> ASYNC_W {
320        ASYNC_W::new(self)
321    }
322    #[doc = "Writes raw bits to the register."]
323    #[inline(always)]
324    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
325        self.0.bits(bits);
326        self
327    }
328}
329#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch0_ctrl](index.html) module"]
330pub struct CH0_CTRL_SPEC;
331impl crate::RegisterSpec for CH0_CTRL_SPEC {
332    type Ux = u32;
333}
334#[doc = "`read()` method returns [ch0_ctrl::R](R) reader structure"]
335impl crate::Readable for CH0_CTRL_SPEC {
336    type Reader = R;
337}
338#[doc = "`write(|w| ..)` method takes [ch0_ctrl::W](W) writer structure"]
339impl crate::Writable for CH0_CTRL_SPEC {
340    type Writer = W;
341}
342#[doc = "`reset()` method sets CH0_CTRL to value 0"]
343impl crate::Resettable for CH0_CTRL_SPEC {
344    #[inline(always)]
345    fn reset_value() -> Self::Ux {
346        0
347    }
348}
efm32zg108_pac/prs/ch0_ctrl.rs

efm32zg108_pac/prs/
ch0_ctrl.rs
