efm32wg990_pac/ebi/
rdtiming2.rs1#[doc = "Register `RDTIMING2` reader"]
2pub struct R(crate::R<RDTIMING2_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<RDTIMING2_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<RDTIMING2_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<RDTIMING2_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `RDTIMING2` writer"]
17pub struct W(crate::W<RDTIMING2_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<RDTIMING2_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<RDTIMING2_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<RDTIMING2_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `RDSETUP` reader - Read Setup Time"]
38pub type RDSETUP_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `RDSETUP` writer - Read Setup Time"]
40pub type RDSETUP_W<'a> = crate::FieldWriter<'a, u32, RDTIMING2_SPEC, u8, u8, 2, 0>;
41#[doc = "Field `RDSTRB` reader - Read Strobe Time"]
42pub type RDSTRB_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `RDSTRB` writer - Read Strobe Time"]
44pub type RDSTRB_W<'a> = crate::FieldWriter<'a, u32, RDTIMING2_SPEC, u8, u8, 6, 8>;
45#[doc = "Field `RDHOLD` reader - Read Hold Time"]
46pub type RDHOLD_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `RDHOLD` writer - Read Hold Time"]
48pub type RDHOLD_W<'a> = crate::FieldWriter<'a, u32, RDTIMING2_SPEC, u8, u8, 2, 16>;
49#[doc = "Field `HALFRE` reader - Half Cycle REn Strobe Duration Enable"]
50pub type HALFRE_R = crate::BitReader<bool>;
51#[doc = "Field `HALFRE` writer - Half Cycle REn Strobe Duration Enable"]
52pub type HALFRE_W<'a> = crate::BitWriter<'a, u32, RDTIMING2_SPEC, bool, 28>;
53#[doc = "Field `PREFETCH` reader - Prefetch Enable"]
54pub type PREFETCH_R = crate::BitReader<bool>;
55#[doc = "Field `PREFETCH` writer - Prefetch Enable"]
56pub type PREFETCH_W<'a> = crate::BitWriter<'a, u32, RDTIMING2_SPEC, bool, 29>;
57#[doc = "Field `PAGEMODE` reader - Page Mode Access Enable"]
58pub type PAGEMODE_R = crate::BitReader<bool>;
59#[doc = "Field `PAGEMODE` writer - Page Mode Access Enable"]
60pub type PAGEMODE_W<'a> = crate::BitWriter<'a, u32, RDTIMING2_SPEC, bool, 30>;
61impl R {
62 #[doc = "Bits 0:1 - Read Setup Time"]
63 #[inline(always)]
64 pub fn rdsetup(&self) -> RDSETUP_R {
65 RDSETUP_R::new((self.bits & 3) as u8)
66 }
67 #[doc = "Bits 8:13 - Read Strobe Time"]
68 #[inline(always)]
69 pub fn rdstrb(&self) -> RDSTRB_R {
70 RDSTRB_R::new(((self.bits >> 8) & 0x3f) as u8)
71 }
72 #[doc = "Bits 16:17 - Read Hold Time"]
73 #[inline(always)]
74 pub fn rdhold(&self) -> RDHOLD_R {
75 RDHOLD_R::new(((self.bits >> 16) & 3) as u8)
76 }
77 #[doc = "Bit 28 - Half Cycle REn Strobe Duration Enable"]
78 #[inline(always)]
79 pub fn halfre(&self) -> HALFRE_R {
80 HALFRE_R::new(((self.bits >> 28) & 1) != 0)
81 }
82 #[doc = "Bit 29 - Prefetch Enable"]
83 #[inline(always)]
84 pub fn prefetch(&self) -> PREFETCH_R {
85 PREFETCH_R::new(((self.bits >> 29) & 1) != 0)
86 }
87 #[doc = "Bit 30 - Page Mode Access Enable"]
88 #[inline(always)]
89 pub fn pagemode(&self) -> PAGEMODE_R {
90 PAGEMODE_R::new(((self.bits >> 30) & 1) != 0)
91 }
92}
93impl W {
94 #[doc = "Bits 0:1 - Read Setup Time"]
95 #[inline(always)]
96 pub fn rdsetup(&mut self) -> RDSETUP_W {
97 RDSETUP_W::new(self)
98 }
99 #[doc = "Bits 8:13 - Read Strobe Time"]
100 #[inline(always)]
101 pub fn rdstrb(&mut self) -> RDSTRB_W {
102 RDSTRB_W::new(self)
103 }
104 #[doc = "Bits 16:17 - Read Hold Time"]
105 #[inline(always)]
106 pub fn rdhold(&mut self) -> RDHOLD_W {
107 RDHOLD_W::new(self)
108 }
109 #[doc = "Bit 28 - Half Cycle REn Strobe Duration Enable"]
110 #[inline(always)]
111 pub fn halfre(&mut self) -> HALFRE_W {
112 HALFRE_W::new(self)
113 }
114 #[doc = "Bit 29 - Prefetch Enable"]
115 #[inline(always)]
116 pub fn prefetch(&mut self) -> PREFETCH_W {
117 PREFETCH_W::new(self)
118 }
119 #[doc = "Bit 30 - Page Mode Access Enable"]
120 #[inline(always)]
121 pub fn pagemode(&mut self) -> PAGEMODE_W {
122 PAGEMODE_W::new(self)
123 }
124 #[doc = "Writes raw bits to the register."]
125 #[inline(always)]
126 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
127 self.0.bits(bits);
128 self
129 }
130}
131#[doc = "Read Timing Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rdtiming2](index.html) module"]
132pub struct RDTIMING2_SPEC;
133impl crate::RegisterSpec for RDTIMING2_SPEC {
134 type Ux = u32;
135}
136#[doc = "`read()` method returns [rdtiming2::R](R) reader structure"]
137impl crate::Readable for RDTIMING2_SPEC {
138 type Reader = R;
139}
140#[doc = "`write(|w| ..)` method takes [rdtiming2::W](W) writer structure"]
141impl crate::Writable for RDTIMING2_SPEC {
142 type Writer = W;
143}
144#[doc = "`reset()` method sets RDTIMING2 to value 0x0003_3f03"]
145impl crate::Resettable for RDTIMING2_SPEC {
146 #[inline(always)]
147 fn reset_value() -> Self::Ux {
148 0x0003_3f03
149 }
150}