efm32wg990_pac/ebi/
addrtiming2.rs1#[doc = "Register `ADDRTIMING2` reader"]
2pub struct R(crate::R<ADDRTIMING2_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<ADDRTIMING2_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<ADDRTIMING2_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<ADDRTIMING2_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `ADDRTIMING2` writer"]
17pub struct W(crate::W<ADDRTIMING2_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<ADDRTIMING2_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<ADDRTIMING2_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<ADDRTIMING2_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `ADDRSETUP` reader - Address Setup Time"]
38pub type ADDRSETUP_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `ADDRSETUP` writer - Address Setup Time"]
40pub type ADDRSETUP_W<'a> = crate::FieldWriter<'a, u32, ADDRTIMING2_SPEC, u8, u8, 2, 0>;
41#[doc = "Field `ADDRHOLD` reader - Address Hold Time"]
42pub type ADDRHOLD_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `ADDRHOLD` writer - Address Hold Time"]
44pub type ADDRHOLD_W<'a> = crate::FieldWriter<'a, u32, ADDRTIMING2_SPEC, u8, u8, 2, 8>;
45#[doc = "Field `HALFALE` reader - Half Cycle ALE Strobe Duration Enable"]
46pub type HALFALE_R = crate::BitReader<bool>;
47#[doc = "Field `HALFALE` writer - Half Cycle ALE Strobe Duration Enable"]
48pub type HALFALE_W<'a> = crate::BitWriter<'a, u32, ADDRTIMING2_SPEC, bool, 28>;
49impl R {
50 #[doc = "Bits 0:1 - Address Setup Time"]
51 #[inline(always)]
52 pub fn addrsetup(&self) -> ADDRSETUP_R {
53 ADDRSETUP_R::new((self.bits & 3) as u8)
54 }
55 #[doc = "Bits 8:9 - Address Hold Time"]
56 #[inline(always)]
57 pub fn addrhold(&self) -> ADDRHOLD_R {
58 ADDRHOLD_R::new(((self.bits >> 8) & 3) as u8)
59 }
60 #[doc = "Bit 28 - Half Cycle ALE Strobe Duration Enable"]
61 #[inline(always)]
62 pub fn halfale(&self) -> HALFALE_R {
63 HALFALE_R::new(((self.bits >> 28) & 1) != 0)
64 }
65}
66impl W {
67 #[doc = "Bits 0:1 - Address Setup Time"]
68 #[inline(always)]
69 pub fn addrsetup(&mut self) -> ADDRSETUP_W {
70 ADDRSETUP_W::new(self)
71 }
72 #[doc = "Bits 8:9 - Address Hold Time"]
73 #[inline(always)]
74 pub fn addrhold(&mut self) -> ADDRHOLD_W {
75 ADDRHOLD_W::new(self)
76 }
77 #[doc = "Bit 28 - Half Cycle ALE Strobe Duration Enable"]
78 #[inline(always)]
79 pub fn halfale(&mut self) -> HALFALE_W {
80 HALFALE_W::new(self)
81 }
82 #[doc = "Writes raw bits to the register."]
83 #[inline(always)]
84 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
85 self.0.bits(bits);
86 self
87 }
88}
89#[doc = "Address Timing Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addrtiming2](index.html) module"]
90pub struct ADDRTIMING2_SPEC;
91impl crate::RegisterSpec for ADDRTIMING2_SPEC {
92 type Ux = u32;
93}
94#[doc = "`read()` method returns [addrtiming2::R](R) reader structure"]
95impl crate::Readable for ADDRTIMING2_SPEC {
96 type Reader = R;
97}
98#[doc = "`write(|w| ..)` method takes [addrtiming2::W](W) writer structure"]
99impl crate::Writable for ADDRTIMING2_SPEC {
100 type Writer = W;
101}
102#[doc = "`reset()` method sets ADDRTIMING2 to value 0x0303"]
103impl crate::Resettable for ADDRTIMING2_SPEC {
104 #[inline(always)]
105 fn reset_value() -> Self::Ux {
106 0x0303
107 }
108}