efm32wg942_pac/usb/
hcfg.rs

1#[doc = "Register `HCFG` reader"]
2pub struct R(crate::R<HCFG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HCFG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HCFG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HCFG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HCFG` writer"]
17pub struct W(crate::W<HCFG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HCFG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HCFG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HCFG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "FS/LS PHY Clock Select\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum FSLSPCLKSEL_A {
41    #[doc = "1: Internal PHY clock is running at 48 MHz (undivided)."]
42    DIV1 = 1,
43    #[doc = "2: Internal PHY clock is running at 6 MHz (48 MHz divided by 8)."]
44    DIV8 = 2,
45}
46impl From<FSLSPCLKSEL_A> for u8 {
47    #[inline(always)]
48    fn from(variant: FSLSPCLKSEL_A) -> Self {
49        variant as _
50    }
51}
52#[doc = "Field `FSLSPCLKSEL` reader - FS/LS PHY Clock Select"]
53pub type FSLSPCLKSEL_R = crate::FieldReader<u8, FSLSPCLKSEL_A>;
54impl FSLSPCLKSEL_R {
55    #[doc = "Get enumerated values variant"]
56    #[inline(always)]
57    pub fn variant(&self) -> Option<FSLSPCLKSEL_A> {
58        match self.bits {
59            1 => Some(FSLSPCLKSEL_A::DIV1),
60            2 => Some(FSLSPCLKSEL_A::DIV8),
61            _ => None,
62        }
63    }
64    #[doc = "Checks if the value of the field is `DIV1`"]
65    #[inline(always)]
66    pub fn is_div1(&self) -> bool {
67        *self == FSLSPCLKSEL_A::DIV1
68    }
69    #[doc = "Checks if the value of the field is `DIV8`"]
70    #[inline(always)]
71    pub fn is_div8(&self) -> bool {
72        *self == FSLSPCLKSEL_A::DIV8
73    }
74}
75#[doc = "Field `FSLSPCLKSEL` writer - FS/LS PHY Clock Select"]
76pub type FSLSPCLKSEL_W<'a> = crate::FieldWriter<'a, u32, HCFG_SPEC, u8, FSLSPCLKSEL_A, 2, 0>;
77impl<'a> FSLSPCLKSEL_W<'a> {
78    #[doc = "Internal PHY clock is running at 48 MHz (undivided)."]
79    #[inline(always)]
80    pub fn div1(self) -> &'a mut W {
81        self.variant(FSLSPCLKSEL_A::DIV1)
82    }
83    #[doc = "Internal PHY clock is running at 6 MHz (48 MHz divided by 8)."]
84    #[inline(always)]
85    pub fn div8(self) -> &'a mut W {
86        self.variant(FSLSPCLKSEL_A::DIV8)
87    }
88}
89#[doc = "Field `FSLSSUPP` reader - FS- and LS-Only Support"]
90pub type FSLSSUPP_R = crate::BitReader<bool>;
91#[doc = "Field `FSLSSUPP` writer - FS- and LS-Only Support"]
92pub type FSLSSUPP_W<'a> = crate::BitWriter<'a, u32, HCFG_SPEC, bool, 2>;
93#[doc = "Field `ENA32KHZS` reader - Enable 32 KHz Suspend mode"]
94pub type ENA32KHZS_R = crate::BitReader<bool>;
95#[doc = "Field `ENA32KHZS` writer - Enable 32 KHz Suspend mode"]
96pub type ENA32KHZS_W<'a> = crate::BitWriter<'a, u32, HCFG_SPEC, bool, 7>;
97#[doc = "Field `RESVALID` reader - Resume Validation Period"]
98pub type RESVALID_R = crate::FieldReader<u8, u8>;
99#[doc = "Field `RESVALID` writer - Resume Validation Period"]
100pub type RESVALID_W<'a> = crate::FieldWriter<'a, u32, HCFG_SPEC, u8, u8, 8, 8>;
101#[doc = "Field `MODECHTIMEN` reader - Mode Change Time"]
102pub type MODECHTIMEN_R = crate::BitReader<bool>;
103#[doc = "Field `MODECHTIMEN` writer - Mode Change Time"]
104pub type MODECHTIMEN_W<'a> = crate::BitWriter<'a, u32, HCFG_SPEC, bool, 31>;
105impl R {
106    #[doc = "Bits 0:1 - FS/LS PHY Clock Select"]
107    #[inline(always)]
108    pub fn fslspclksel(&self) -> FSLSPCLKSEL_R {
109        FSLSPCLKSEL_R::new((self.bits & 3) as u8)
110    }
111    #[doc = "Bit 2 - FS- and LS-Only Support"]
112    #[inline(always)]
113    pub fn fslssupp(&self) -> FSLSSUPP_R {
114        FSLSSUPP_R::new(((self.bits >> 2) & 1) != 0)
115    }
116    #[doc = "Bit 7 - Enable 32 KHz Suspend mode"]
117    #[inline(always)]
118    pub fn ena32khzs(&self) -> ENA32KHZS_R {
119        ENA32KHZS_R::new(((self.bits >> 7) & 1) != 0)
120    }
121    #[doc = "Bits 8:15 - Resume Validation Period"]
122    #[inline(always)]
123    pub fn resvalid(&self) -> RESVALID_R {
124        RESVALID_R::new(((self.bits >> 8) & 0xff) as u8)
125    }
126    #[doc = "Bit 31 - Mode Change Time"]
127    #[inline(always)]
128    pub fn modechtimen(&self) -> MODECHTIMEN_R {
129        MODECHTIMEN_R::new(((self.bits >> 31) & 1) != 0)
130    }
131}
132impl W {
133    #[doc = "Bits 0:1 - FS/LS PHY Clock Select"]
134    #[inline(always)]
135    pub fn fslspclksel(&mut self) -> FSLSPCLKSEL_W {
136        FSLSPCLKSEL_W::new(self)
137    }
138    #[doc = "Bit 2 - FS- and LS-Only Support"]
139    #[inline(always)]
140    pub fn fslssupp(&mut self) -> FSLSSUPP_W {
141        FSLSSUPP_W::new(self)
142    }
143    #[doc = "Bit 7 - Enable 32 KHz Suspend mode"]
144    #[inline(always)]
145    pub fn ena32khzs(&mut self) -> ENA32KHZS_W {
146        ENA32KHZS_W::new(self)
147    }
148    #[doc = "Bits 8:15 - Resume Validation Period"]
149    #[inline(always)]
150    pub fn resvalid(&mut self) -> RESVALID_W {
151        RESVALID_W::new(self)
152    }
153    #[doc = "Bit 31 - Mode Change Time"]
154    #[inline(always)]
155    pub fn modechtimen(&mut self) -> MODECHTIMEN_W {
156        MODECHTIMEN_W::new(self)
157    }
158    #[doc = "Writes raw bits to the register."]
159    #[inline(always)]
160    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
161        self.0.bits(bits);
162        self
163    }
164}
165#[doc = "Host Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcfg](index.html) module"]
166pub struct HCFG_SPEC;
167impl crate::RegisterSpec for HCFG_SPEC {
168    type Ux = u32;
169}
170#[doc = "`read()` method returns [hcfg::R](R) reader structure"]
171impl crate::Readable for HCFG_SPEC {
172    type Reader = R;
173}
174#[doc = "`write(|w| ..)` method takes [hcfg::W](W) writer structure"]
175impl crate::Writable for HCFG_SPEC {
176    type Writer = W;
177}
178#[doc = "`reset()` method sets HCFG to value 0x0020_0000"]
179impl crate::Resettable for HCFG_SPEC {
180    #[inline(always)]
181    fn reset_value() -> Self::Ux {
182        0x0020_0000
183    }
184}
efm32wg942_pac/usb/hcfg.rs

efm32wg942_pac/usb/
hcfg.rs
