efm32wg895_pac/prs/
ch11_ctrl.rs

1#[doc = "Register `CH11_CTRL` reader"]
2pub struct R(crate::R<CH11_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH11_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH11_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH11_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH11_CTRL` writer"]
17pub struct W(crate::W<CH11_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH11_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH11_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH11_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH11_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Voltage Comparator"]
48    VCMP = 1,
49    #[doc = "2: Analog Comparator 0"]
50    ACMP0 = 2,
51    #[doc = "3: Analog Comparator 1"]
52    ACMP1 = 3,
53    #[doc = "6: Digital to Analog Converter 0"]
54    DAC0 = 6,
55    #[doc = "8: Analog to Digital Converter 0"]
56    ADC0 = 8,
57    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
58    USART0 = 16,
59    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
60    USART1 = 17,
61    #[doc = "18: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
62    USART2 = 18,
63    #[doc = "28: Timer 0"]
64    TIMER0 = 28,
65    #[doc = "29: Timer 1"]
66    TIMER1 = 29,
67    #[doc = "30: Timer 2"]
68    TIMER2 = 30,
69    #[doc = "31: Timer 3"]
70    TIMER3 = 31,
71    #[doc = "40: Real-Time Counter"]
72    RTC = 40,
73    #[doc = "41: Universal Asynchronous Receiver/Transmitter 0"]
74    UART0 = 41,
75    #[doc = "42: Universal Asynchronous Receiver/Transmitter 1"]
76    UART1 = 42,
77    #[doc = "48: General purpose Input/Output"]
78    GPIOL = 48,
79    #[doc = "49: General purpose Input/Output"]
80    GPIOH = 49,
81    #[doc = "52: Low Energy Timer 0"]
82    LETIMER0 = 52,
83    #[doc = "55: Backup RTC"]
84    BURTC = 55,
85    #[doc = "57: Low Energy Sensor Interface"]
86    LESENSEL = 57,
87    #[doc = "58: Low Energy Sensor Interface"]
88    LESENSEH = 58,
89    #[doc = "59: Low Energy Sensor Interface"]
90    LESENSED = 59,
91}
92impl From<SOURCESEL_A> for u8 {
93    #[inline(always)]
94    fn from(variant: SOURCESEL_A) -> Self {
95        variant as _
96    }
97}
98#[doc = "Field `SOURCESEL` reader - Source Select"]
99pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
100impl SOURCESEL_R {
101    #[doc = "Get enumerated values variant"]
102    #[inline(always)]
103    pub fn variant(&self) -> Option<SOURCESEL_A> {
104        match self.bits {
105            0 => Some(SOURCESEL_A::NONE),
106            1 => Some(SOURCESEL_A::VCMP),
107            2 => Some(SOURCESEL_A::ACMP0),
108            3 => Some(SOURCESEL_A::ACMP1),
109            6 => Some(SOURCESEL_A::DAC0),
110            8 => Some(SOURCESEL_A::ADC0),
111            16 => Some(SOURCESEL_A::USART0),
112            17 => Some(SOURCESEL_A::USART1),
113            18 => Some(SOURCESEL_A::USART2),
114            28 => Some(SOURCESEL_A::TIMER0),
115            29 => Some(SOURCESEL_A::TIMER1),
116            30 => Some(SOURCESEL_A::TIMER2),
117            31 => Some(SOURCESEL_A::TIMER3),
118            40 => Some(SOURCESEL_A::RTC),
119            41 => Some(SOURCESEL_A::UART0),
120            42 => Some(SOURCESEL_A::UART1),
121            48 => Some(SOURCESEL_A::GPIOL),
122            49 => Some(SOURCESEL_A::GPIOH),
123            52 => Some(SOURCESEL_A::LETIMER0),
124            55 => Some(SOURCESEL_A::BURTC),
125            57 => Some(SOURCESEL_A::LESENSEL),
126            58 => Some(SOURCESEL_A::LESENSEH),
127            59 => Some(SOURCESEL_A::LESENSED),
128            _ => None,
129        }
130    }
131    #[doc = "Checks if the value of the field is `NONE`"]
132    #[inline(always)]
133    pub fn is_none(&self) -> bool {
134        *self == SOURCESEL_A::NONE
135    }
136    #[doc = "Checks if the value of the field is `VCMP`"]
137    #[inline(always)]
138    pub fn is_vcmp(&self) -> bool {
139        *self == SOURCESEL_A::VCMP
140    }
141    #[doc = "Checks if the value of the field is `ACMP0`"]
142    #[inline(always)]
143    pub fn is_acmp0(&self) -> bool {
144        *self == SOURCESEL_A::ACMP0
145    }
146    #[doc = "Checks if the value of the field is `ACMP1`"]
147    #[inline(always)]
148    pub fn is_acmp1(&self) -> bool {
149        *self == SOURCESEL_A::ACMP1
150    }
151    #[doc = "Checks if the value of the field is `DAC0`"]
152    #[inline(always)]
153    pub fn is_dac0(&self) -> bool {
154        *self == SOURCESEL_A::DAC0
155    }
156    #[doc = "Checks if the value of the field is `ADC0`"]
157    #[inline(always)]
158    pub fn is_adc0(&self) -> bool {
159        *self == SOURCESEL_A::ADC0
160    }
161    #[doc = "Checks if the value of the field is `USART0`"]
162    #[inline(always)]
163    pub fn is_usart0(&self) -> bool {
164        *self == SOURCESEL_A::USART0
165    }
166    #[doc = "Checks if the value of the field is `USART1`"]
167    #[inline(always)]
168    pub fn is_usart1(&self) -> bool {
169        *self == SOURCESEL_A::USART1
170    }
171    #[doc = "Checks if the value of the field is `USART2`"]
172    #[inline(always)]
173    pub fn is_usart2(&self) -> bool {
174        *self == SOURCESEL_A::USART2
175    }
176    #[doc = "Checks if the value of the field is `TIMER0`"]
177    #[inline(always)]
178    pub fn is_timer0(&self) -> bool {
179        *self == SOURCESEL_A::TIMER0
180    }
181    #[doc = "Checks if the value of the field is `TIMER1`"]
182    #[inline(always)]
183    pub fn is_timer1(&self) -> bool {
184        *self == SOURCESEL_A::TIMER1
185    }
186    #[doc = "Checks if the value of the field is `TIMER2`"]
187    #[inline(always)]
188    pub fn is_timer2(&self) -> bool {
189        *self == SOURCESEL_A::TIMER2
190    }
191    #[doc = "Checks if the value of the field is `TIMER3`"]
192    #[inline(always)]
193    pub fn is_timer3(&self) -> bool {
194        *self == SOURCESEL_A::TIMER3
195    }
196    #[doc = "Checks if the value of the field is `RTC`"]
197    #[inline(always)]
198    pub fn is_rtc(&self) -> bool {
199        *self == SOURCESEL_A::RTC
200    }
201    #[doc = "Checks if the value of the field is `UART0`"]
202    #[inline(always)]
203    pub fn is_uart0(&self) -> bool {
204        *self == SOURCESEL_A::UART0
205    }
206    #[doc = "Checks if the value of the field is `UART1`"]
207    #[inline(always)]
208    pub fn is_uart1(&self) -> bool {
209        *self == SOURCESEL_A::UART1
210    }
211    #[doc = "Checks if the value of the field is `GPIOL`"]
212    #[inline(always)]
213    pub fn is_gpiol(&self) -> bool {
214        *self == SOURCESEL_A::GPIOL
215    }
216    #[doc = "Checks if the value of the field is `GPIOH`"]
217    #[inline(always)]
218    pub fn is_gpioh(&self) -> bool {
219        *self == SOURCESEL_A::GPIOH
220    }
221    #[doc = "Checks if the value of the field is `LETIMER0`"]
222    #[inline(always)]
223    pub fn is_letimer0(&self) -> bool {
224        *self == SOURCESEL_A::LETIMER0
225    }
226    #[doc = "Checks if the value of the field is `BURTC`"]
227    #[inline(always)]
228    pub fn is_burtc(&self) -> bool {
229        *self == SOURCESEL_A::BURTC
230    }
231    #[doc = "Checks if the value of the field is `LESENSEL`"]
232    #[inline(always)]
233    pub fn is_lesensel(&self) -> bool {
234        *self == SOURCESEL_A::LESENSEL
235    }
236    #[doc = "Checks if the value of the field is `LESENSEH`"]
237    #[inline(always)]
238    pub fn is_lesenseh(&self) -> bool {
239        *self == SOURCESEL_A::LESENSEH
240    }
241    #[doc = "Checks if the value of the field is `LESENSED`"]
242    #[inline(always)]
243    pub fn is_lesensed(&self) -> bool {
244        *self == SOURCESEL_A::LESENSED
245    }
246}
247#[doc = "Field `SOURCESEL` writer - Source Select"]
248pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH11_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
249impl<'a> SOURCESEL_W<'a> {
250    #[doc = "No source selected"]
251    #[inline(always)]
252    pub fn none(self) -> &'a mut W {
253        self.variant(SOURCESEL_A::NONE)
254    }
255    #[doc = "Voltage Comparator"]
256    #[inline(always)]
257    pub fn vcmp(self) -> &'a mut W {
258        self.variant(SOURCESEL_A::VCMP)
259    }
260    #[doc = "Analog Comparator 0"]
261    #[inline(always)]
262    pub fn acmp0(self) -> &'a mut W {
263        self.variant(SOURCESEL_A::ACMP0)
264    }
265    #[doc = "Analog Comparator 1"]
266    #[inline(always)]
267    pub fn acmp1(self) -> &'a mut W {
268        self.variant(SOURCESEL_A::ACMP1)
269    }
270    #[doc = "Digital to Analog Converter 0"]
271    #[inline(always)]
272    pub fn dac0(self) -> &'a mut W {
273        self.variant(SOURCESEL_A::DAC0)
274    }
275    #[doc = "Analog to Digital Converter 0"]
276    #[inline(always)]
277    pub fn adc0(self) -> &'a mut W {
278        self.variant(SOURCESEL_A::ADC0)
279    }
280    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
281    #[inline(always)]
282    pub fn usart0(self) -> &'a mut W {
283        self.variant(SOURCESEL_A::USART0)
284    }
285    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
286    #[inline(always)]
287    pub fn usart1(self) -> &'a mut W {
288        self.variant(SOURCESEL_A::USART1)
289    }
290    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
291    #[inline(always)]
292    pub fn usart2(self) -> &'a mut W {
293        self.variant(SOURCESEL_A::USART2)
294    }
295    #[doc = "Timer 0"]
296    #[inline(always)]
297    pub fn timer0(self) -> &'a mut W {
298        self.variant(SOURCESEL_A::TIMER0)
299    }
300    #[doc = "Timer 1"]
301    #[inline(always)]
302    pub fn timer1(self) -> &'a mut W {
303        self.variant(SOURCESEL_A::TIMER1)
304    }
305    #[doc = "Timer 2"]
306    #[inline(always)]
307    pub fn timer2(self) -> &'a mut W {
308        self.variant(SOURCESEL_A::TIMER2)
309    }
310    #[doc = "Timer 3"]
311    #[inline(always)]
312    pub fn timer3(self) -> &'a mut W {
313        self.variant(SOURCESEL_A::TIMER3)
314    }
315    #[doc = "Real-Time Counter"]
316    #[inline(always)]
317    pub fn rtc(self) -> &'a mut W {
318        self.variant(SOURCESEL_A::RTC)
319    }
320    #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
321    #[inline(always)]
322    pub fn uart0(self) -> &'a mut W {
323        self.variant(SOURCESEL_A::UART0)
324    }
325    #[doc = "Universal Asynchronous Receiver/Transmitter 1"]
326    #[inline(always)]
327    pub fn uart1(self) -> &'a mut W {
328        self.variant(SOURCESEL_A::UART1)
329    }
330    #[doc = "General purpose Input/Output"]
331    #[inline(always)]
332    pub fn gpiol(self) -> &'a mut W {
333        self.variant(SOURCESEL_A::GPIOL)
334    }
335    #[doc = "General purpose Input/Output"]
336    #[inline(always)]
337    pub fn gpioh(self) -> &'a mut W {
338        self.variant(SOURCESEL_A::GPIOH)
339    }
340    #[doc = "Low Energy Timer 0"]
341    #[inline(always)]
342    pub fn letimer0(self) -> &'a mut W {
343        self.variant(SOURCESEL_A::LETIMER0)
344    }
345    #[doc = "Backup RTC"]
346    #[inline(always)]
347    pub fn burtc(self) -> &'a mut W {
348        self.variant(SOURCESEL_A::BURTC)
349    }
350    #[doc = "Low Energy Sensor Interface"]
351    #[inline(always)]
352    pub fn lesensel(self) -> &'a mut W {
353        self.variant(SOURCESEL_A::LESENSEL)
354    }
355    #[doc = "Low Energy Sensor Interface"]
356    #[inline(always)]
357    pub fn lesenseh(self) -> &'a mut W {
358        self.variant(SOURCESEL_A::LESENSEH)
359    }
360    #[doc = "Low Energy Sensor Interface"]
361    #[inline(always)]
362    pub fn lesensed(self) -> &'a mut W {
363        self.variant(SOURCESEL_A::LESENSED)
364    }
365}
366#[doc = "Edge Detect Select\n\nValue on reset: 0"]
367#[derive(Clone, Copy, Debug, PartialEq)]
368#[repr(u8)]
369pub enum EDSEL_A {
370    #[doc = "0: Signal is left as it is"]
371    OFF = 0,
372    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
373    POSEDGE = 1,
374    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
375    NEGEDGE = 2,
376    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
377    BOTHEDGES = 3,
378}
379impl From<EDSEL_A> for u8 {
380    #[inline(always)]
381    fn from(variant: EDSEL_A) -> Self {
382        variant as _
383    }
384}
385#[doc = "Field `EDSEL` reader - Edge Detect Select"]
386pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
387impl EDSEL_R {
388    #[doc = "Get enumerated values variant"]
389    #[inline(always)]
390    pub fn variant(&self) -> EDSEL_A {
391        match self.bits {
392            0 => EDSEL_A::OFF,
393            1 => EDSEL_A::POSEDGE,
394            2 => EDSEL_A::NEGEDGE,
395            3 => EDSEL_A::BOTHEDGES,
396            _ => unreachable!(),
397        }
398    }
399    #[doc = "Checks if the value of the field is `OFF`"]
400    #[inline(always)]
401    pub fn is_off(&self) -> bool {
402        *self == EDSEL_A::OFF
403    }
404    #[doc = "Checks if the value of the field is `POSEDGE`"]
405    #[inline(always)]
406    pub fn is_posedge(&self) -> bool {
407        *self == EDSEL_A::POSEDGE
408    }
409    #[doc = "Checks if the value of the field is `NEGEDGE`"]
410    #[inline(always)]
411    pub fn is_negedge(&self) -> bool {
412        *self == EDSEL_A::NEGEDGE
413    }
414    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
415    #[inline(always)]
416    pub fn is_bothedges(&self) -> bool {
417        *self == EDSEL_A::BOTHEDGES
418    }
419}
420#[doc = "Field `EDSEL` writer - Edge Detect Select"]
421pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH11_CTRL_SPEC, u8, EDSEL_A, 2, 24>;
422impl<'a> EDSEL_W<'a> {
423    #[doc = "Signal is left as it is"]
424    #[inline(always)]
425    pub fn off(self) -> &'a mut W {
426        self.variant(EDSEL_A::OFF)
427    }
428    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
429    #[inline(always)]
430    pub fn posedge(self) -> &'a mut W {
431        self.variant(EDSEL_A::POSEDGE)
432    }
433    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
434    #[inline(always)]
435    pub fn negedge(self) -> &'a mut W {
436        self.variant(EDSEL_A::NEGEDGE)
437    }
438    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
439    #[inline(always)]
440    pub fn bothedges(self) -> &'a mut W {
441        self.variant(EDSEL_A::BOTHEDGES)
442    }
443}
444#[doc = "Field `ASYNC` reader - Asynchronous reflex"]
445pub type ASYNC_R = crate::BitReader<bool>;
446#[doc = "Field `ASYNC` writer - Asynchronous reflex"]
447pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH11_CTRL_SPEC, bool, 28>;
448impl R {
449    #[doc = "Bits 0:2 - Signal Select"]
450    #[inline(always)]
451    pub fn sigsel(&self) -> SIGSEL_R {
452        SIGSEL_R::new((self.bits & 7) as u8)
453    }
454    #[doc = "Bits 16:21 - Source Select"]
455    #[inline(always)]
456    pub fn sourcesel(&self) -> SOURCESEL_R {
457        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
458    }
459    #[doc = "Bits 24:25 - Edge Detect Select"]
460    #[inline(always)]
461    pub fn edsel(&self) -> EDSEL_R {
462        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
463    }
464    #[doc = "Bit 28 - Asynchronous reflex"]
465    #[inline(always)]
466    pub fn async_(&self) -> ASYNC_R {
467        ASYNC_R::new(((self.bits >> 28) & 1) != 0)
468    }
469}
470impl W {
471    #[doc = "Bits 0:2 - Signal Select"]
472    #[inline(always)]
473    pub fn sigsel(&mut self) -> SIGSEL_W {
474        SIGSEL_W::new(self)
475    }
476    #[doc = "Bits 16:21 - Source Select"]
477    #[inline(always)]
478    pub fn sourcesel(&mut self) -> SOURCESEL_W {
479        SOURCESEL_W::new(self)
480    }
481    #[doc = "Bits 24:25 - Edge Detect Select"]
482    #[inline(always)]
483    pub fn edsel(&mut self) -> EDSEL_W {
484        EDSEL_W::new(self)
485    }
486    #[doc = "Bit 28 - Asynchronous reflex"]
487    #[inline(always)]
488    pub fn async_(&mut self) -> ASYNC_W {
489        ASYNC_W::new(self)
490    }
491    #[doc = "Writes raw bits to the register."]
492    #[inline(always)]
493    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
494        self.0.bits(bits);
495        self
496    }
497}
498#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch11_ctrl](index.html) module"]
499pub struct CH11_CTRL_SPEC;
500impl crate::RegisterSpec for CH11_CTRL_SPEC {
501    type Ux = u32;
502}
503#[doc = "`read()` method returns [ch11_ctrl::R](R) reader structure"]
504impl crate::Readable for CH11_CTRL_SPEC {
505    type Reader = R;
506}
507#[doc = "`write(|w| ..)` method takes [ch11_ctrl::W](W) writer structure"]
508impl crate::Writable for CH11_CTRL_SPEC {
509    type Writer = W;
510}
511#[doc = "`reset()` method sets CH11_CTRL to value 0"]
512impl crate::Resettable for CH11_CTRL_SPEC {
513    #[inline(always)]
514    fn reset_value() -> Self::Ux {
515        0
516    }
517}
efm32wg895_pac/prs/ch11_ctrl.rs

efm32wg895_pac/prs/
ch11_ctrl.rs
