efm32wg380_pac/usb/
hc12_char.rs

1#[doc = "Register `HC12_CHAR` reader"]
2pub struct R(crate::R<HC12_CHAR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HC12_CHAR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HC12_CHAR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HC12_CHAR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HC12_CHAR` writer"]
17pub struct W(crate::W<HC12_CHAR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HC12_CHAR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HC12_CHAR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HC12_CHAR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MPS` reader - Maximum Packet Size"]
38pub type MPS_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `MPS` writer - Maximum Packet Size"]
40pub type MPS_W<'a> = crate::FieldWriter<'a, u32, HC12_CHAR_SPEC, u16, u16, 11, 0>;
41#[doc = "Field `EPNUM` reader - Endpoint Number"]
42pub type EPNUM_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `EPNUM` writer - Endpoint Number"]
44pub type EPNUM_W<'a> = crate::FieldWriter<'a, u32, HC12_CHAR_SPEC, u8, u8, 4, 11>;
45#[doc = "Field `EPDIR` reader - Endpoint Direction"]
46pub type EPDIR_R = crate::BitReader<bool>;
47#[doc = "Field `EPDIR` writer - Endpoint Direction"]
48pub type EPDIR_W<'a> = crate::BitWriter<'a, u32, HC12_CHAR_SPEC, bool, 15>;
49#[doc = "Field `LSPDDEV` reader - Low-Speed Device"]
50pub type LSPDDEV_R = crate::BitReader<bool>;
51#[doc = "Field `LSPDDEV` writer - Low-Speed Device"]
52pub type LSPDDEV_W<'a> = crate::BitWriter<'a, u32, HC12_CHAR_SPEC, bool, 17>;
53#[doc = "Endpoint Type\n\nValue on reset: 0"]
54#[derive(Clone, Copy, Debug, PartialEq)]
55#[repr(u8)]
56pub enum EPTYPE_A {
57    #[doc = "0: Control endpoint."]
58    CONTROL = 0,
59    #[doc = "1: Isochronous endpoint."]
60    ISO = 1,
61    #[doc = "2: Bulk endpoint."]
62    BULK = 2,
63    #[doc = "3: Interrupt endpoint."]
64    INT = 3,
65}
66impl From<EPTYPE_A> for u8 {
67    #[inline(always)]
68    fn from(variant: EPTYPE_A) -> Self {
69        variant as _
70    }
71}
72#[doc = "Field `EPTYPE` reader - Endpoint Type"]
73pub type EPTYPE_R = crate::FieldReader<u8, EPTYPE_A>;
74impl EPTYPE_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub fn variant(&self) -> EPTYPE_A {
78        match self.bits {
79            0 => EPTYPE_A::CONTROL,
80            1 => EPTYPE_A::ISO,
81            2 => EPTYPE_A::BULK,
82            3 => EPTYPE_A::INT,
83            _ => unreachable!(),
84        }
85    }
86    #[doc = "Checks if the value of the field is `CONTROL`"]
87    #[inline(always)]
88    pub fn is_control(&self) -> bool {
89        *self == EPTYPE_A::CONTROL
90    }
91    #[doc = "Checks if the value of the field is `ISO`"]
92    #[inline(always)]
93    pub fn is_iso(&self) -> bool {
94        *self == EPTYPE_A::ISO
95    }
96    #[doc = "Checks if the value of the field is `BULK`"]
97    #[inline(always)]
98    pub fn is_bulk(&self) -> bool {
99        *self == EPTYPE_A::BULK
100    }
101    #[doc = "Checks if the value of the field is `INT`"]
102    #[inline(always)]
103    pub fn is_int(&self) -> bool {
104        *self == EPTYPE_A::INT
105    }
106}
107#[doc = "Field `EPTYPE` writer - Endpoint Type"]
108pub type EPTYPE_W<'a> = crate::FieldWriterSafe<'a, u32, HC12_CHAR_SPEC, u8, EPTYPE_A, 2, 18>;
109impl<'a> EPTYPE_W<'a> {
110    #[doc = "Control endpoint."]
111    #[inline(always)]
112    pub fn control(self) -> &'a mut W {
113        self.variant(EPTYPE_A::CONTROL)
114    }
115    #[doc = "Isochronous endpoint."]
116    #[inline(always)]
117    pub fn iso(self) -> &'a mut W {
118        self.variant(EPTYPE_A::ISO)
119    }
120    #[doc = "Bulk endpoint."]
121    #[inline(always)]
122    pub fn bulk(self) -> &'a mut W {
123        self.variant(EPTYPE_A::BULK)
124    }
125    #[doc = "Interrupt endpoint."]
126    #[inline(always)]
127    pub fn int(self) -> &'a mut W {
128        self.variant(EPTYPE_A::INT)
129    }
130}
131#[doc = "Field `MC` reader - Multi Count"]
132pub type MC_R = crate::FieldReader<u8, u8>;
133#[doc = "Field `MC` writer - Multi Count"]
134pub type MC_W<'a> = crate::FieldWriter<'a, u32, HC12_CHAR_SPEC, u8, u8, 2, 20>;
135#[doc = "Field `DEVADDR` reader - Device Address"]
136pub type DEVADDR_R = crate::FieldReader<u8, u8>;
137#[doc = "Field `DEVADDR` writer - Device Address"]
138pub type DEVADDR_W<'a> = crate::FieldWriter<'a, u32, HC12_CHAR_SPEC, u8, u8, 7, 22>;
139#[doc = "Field `ODDFRM` reader - Odd Frame"]
140pub type ODDFRM_R = crate::BitReader<bool>;
141#[doc = "Field `ODDFRM` writer - Odd Frame"]
142pub type ODDFRM_W<'a> = crate::BitWriter<'a, u32, HC12_CHAR_SPEC, bool, 29>;
143#[doc = "Field `CHDIS` reader - Channel Disable"]
144pub type CHDIS_R = crate::BitReader<bool>;
145#[doc = "Field `CHDIS` writer - Channel Disable"]
146pub type CHDIS_W<'a> = crate::BitWriter<'a, u32, HC12_CHAR_SPEC, bool, 30>;
147#[doc = "Field `CHENA` reader - Channel Enable"]
148pub type CHENA_R = crate::BitReader<bool>;
149#[doc = "Field `CHENA` writer - Channel Enable"]
150pub type CHENA_W<'a> = crate::BitWriter<'a, u32, HC12_CHAR_SPEC, bool, 31>;
151impl R {
152    #[doc = "Bits 0:10 - Maximum Packet Size"]
153    #[inline(always)]
154    pub fn mps(&self) -> MPS_R {
155        MPS_R::new((self.bits & 0x07ff) as u16)
156    }
157    #[doc = "Bits 11:14 - Endpoint Number"]
158    #[inline(always)]
159    pub fn epnum(&self) -> EPNUM_R {
160        EPNUM_R::new(((self.bits >> 11) & 0x0f) as u8)
161    }
162    #[doc = "Bit 15 - Endpoint Direction"]
163    #[inline(always)]
164    pub fn epdir(&self) -> EPDIR_R {
165        EPDIR_R::new(((self.bits >> 15) & 1) != 0)
166    }
167    #[doc = "Bit 17 - Low-Speed Device"]
168    #[inline(always)]
169    pub fn lspddev(&self) -> LSPDDEV_R {
170        LSPDDEV_R::new(((self.bits >> 17) & 1) != 0)
171    }
172    #[doc = "Bits 18:19 - Endpoint Type"]
173    #[inline(always)]
174    pub fn eptype(&self) -> EPTYPE_R {
175        EPTYPE_R::new(((self.bits >> 18) & 3) as u8)
176    }
177    #[doc = "Bits 20:21 - Multi Count"]
178    #[inline(always)]
179    pub fn mc(&self) -> MC_R {
180        MC_R::new(((self.bits >> 20) & 3) as u8)
181    }
182    #[doc = "Bits 22:28 - Device Address"]
183    #[inline(always)]
184    pub fn devaddr(&self) -> DEVADDR_R {
185        DEVADDR_R::new(((self.bits >> 22) & 0x7f) as u8)
186    }
187    #[doc = "Bit 29 - Odd Frame"]
188    #[inline(always)]
189    pub fn oddfrm(&self) -> ODDFRM_R {
190        ODDFRM_R::new(((self.bits >> 29) & 1) != 0)
191    }
192    #[doc = "Bit 30 - Channel Disable"]
193    #[inline(always)]
194    pub fn chdis(&self) -> CHDIS_R {
195        CHDIS_R::new(((self.bits >> 30) & 1) != 0)
196    }
197    #[doc = "Bit 31 - Channel Enable"]
198    #[inline(always)]
199    pub fn chena(&self) -> CHENA_R {
200        CHENA_R::new(((self.bits >> 31) & 1) != 0)
201    }
202}
203impl W {
204    #[doc = "Bits 0:10 - Maximum Packet Size"]
205    #[inline(always)]
206    pub fn mps(&mut self) -> MPS_W {
207        MPS_W::new(self)
208    }
209    #[doc = "Bits 11:14 - Endpoint Number"]
210    #[inline(always)]
211    pub fn epnum(&mut self) -> EPNUM_W {
212        EPNUM_W::new(self)
213    }
214    #[doc = "Bit 15 - Endpoint Direction"]
215    #[inline(always)]
216    pub fn epdir(&mut self) -> EPDIR_W {
217        EPDIR_W::new(self)
218    }
219    #[doc = "Bit 17 - Low-Speed Device"]
220    #[inline(always)]
221    pub fn lspddev(&mut self) -> LSPDDEV_W {
222        LSPDDEV_W::new(self)
223    }
224    #[doc = "Bits 18:19 - Endpoint Type"]
225    #[inline(always)]
226    pub fn eptype(&mut self) -> EPTYPE_W {
227        EPTYPE_W::new(self)
228    }
229    #[doc = "Bits 20:21 - Multi Count"]
230    #[inline(always)]
231    pub fn mc(&mut self) -> MC_W {
232        MC_W::new(self)
233    }
234    #[doc = "Bits 22:28 - Device Address"]
235    #[inline(always)]
236    pub fn devaddr(&mut self) -> DEVADDR_W {
237        DEVADDR_W::new(self)
238    }
239    #[doc = "Bit 29 - Odd Frame"]
240    #[inline(always)]
241    pub fn oddfrm(&mut self) -> ODDFRM_W {
242        ODDFRM_W::new(self)
243    }
244    #[doc = "Bit 30 - Channel Disable"]
245    #[inline(always)]
246    pub fn chdis(&mut self) -> CHDIS_W {
247        CHDIS_W::new(self)
248    }
249    #[doc = "Bit 31 - Channel Enable"]
250    #[inline(always)]
251    pub fn chena(&mut self) -> CHENA_W {
252        CHENA_W::new(self)
253    }
254    #[doc = "Writes raw bits to the register."]
255    #[inline(always)]
256    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
257        self.0.bits(bits);
258        self
259    }
260}
261#[doc = "Host Channel x Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc12_char](index.html) module"]
262pub struct HC12_CHAR_SPEC;
263impl crate::RegisterSpec for HC12_CHAR_SPEC {
264    type Ux = u32;
265}
266#[doc = "`read()` method returns [hc12_char::R](R) reader structure"]
267impl crate::Readable for HC12_CHAR_SPEC {
268    type Reader = R;
269}
270#[doc = "`write(|w| ..)` method takes [hc12_char::W](W) writer structure"]
271impl crate::Writable for HC12_CHAR_SPEC {
272    type Writer = W;
273}
274#[doc = "`reset()` method sets HC12_CHAR to value 0"]
275impl crate::Resettable for HC12_CHAR_SPEC {
276    #[inline(always)]
277    fn reset_value() -> Self::Ux {
278        0
279    }
280}
efm32wg380_pac/usb/hc12_char.rs

efm32wg380_pac/usb/
hc12_char.rs
