efm32wg230_pac/usart0/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SYNC` reader - USART Synchronous Mode"]
38pub type SYNC_R = crate::BitReader<bool>;
39#[doc = "Field `SYNC` writer - USART Synchronous Mode"]
40pub type SYNC_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 0>;
41#[doc = "Field `LOOPBK` reader - Loopback Enable"]
42pub type LOOPBK_R = crate::BitReader<bool>;
43#[doc = "Field `LOOPBK` writer - Loopback Enable"]
44pub type LOOPBK_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 1>;
45#[doc = "Field `CCEN` reader - Collision Check Enable"]
46pub type CCEN_R = crate::BitReader<bool>;
47#[doc = "Field `CCEN` writer - Collision Check Enable"]
48pub type CCEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 2>;
49#[doc = "Field `MPM` reader - Multi-Processor Mode"]
50pub type MPM_R = crate::BitReader<bool>;
51#[doc = "Field `MPM` writer - Multi-Processor Mode"]
52pub type MPM_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 3>;
53#[doc = "Field `MPAB` reader - Multi-Processor Address-Bit"]
54pub type MPAB_R = crate::BitReader<bool>;
55#[doc = "Field `MPAB` writer - Multi-Processor Address-Bit"]
56pub type MPAB_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 4>;
57#[doc = "Oversampling\n\nValue on reset: 0"]
58#[derive(Clone, Copy, Debug, PartialEq)]
59#[repr(u8)]
60pub enum OVS_A {
61    #[doc = "0: Regular UART mode with 16X oversampling in asynchronous mode"]
62    X16 = 0,
63    #[doc = "1: Double speed with 8X oversampling in asynchronous mode"]
64    X8 = 1,
65    #[doc = "2: 6X oversampling in asynchronous mode"]
66    X6 = 2,
67    #[doc = "3: Quadruple speed with 4X oversampling in asynchronous mode"]
68    X4 = 3,
69}
70impl From<OVS_A> for u8 {
71    #[inline(always)]
72    fn from(variant: OVS_A) -> Self {
73        variant as _
74    }
75}
76#[doc = "Field `OVS` reader - Oversampling"]
77pub type OVS_R = crate::FieldReader<u8, OVS_A>;
78impl OVS_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub fn variant(&self) -> OVS_A {
82        match self.bits {
83            0 => OVS_A::X16,
84            1 => OVS_A::X8,
85            2 => OVS_A::X6,
86            3 => OVS_A::X4,
87            _ => unreachable!(),
88        }
89    }
90    #[doc = "Checks if the value of the field is `X16`"]
91    #[inline(always)]
92    pub fn is_x16(&self) -> bool {
93        *self == OVS_A::X16
94    }
95    #[doc = "Checks if the value of the field is `X8`"]
96    #[inline(always)]
97    pub fn is_x8(&self) -> bool {
98        *self == OVS_A::X8
99    }
100    #[doc = "Checks if the value of the field is `X6`"]
101    #[inline(always)]
102    pub fn is_x6(&self) -> bool {
103        *self == OVS_A::X6
104    }
105    #[doc = "Checks if the value of the field is `X4`"]
106    #[inline(always)]
107    pub fn is_x4(&self) -> bool {
108        *self == OVS_A::X4
109    }
110}
111#[doc = "Field `OVS` writer - Oversampling"]
112pub type OVS_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, OVS_A, 2, 5>;
113impl<'a> OVS_W<'a> {
114    #[doc = "Regular UART mode with 16X oversampling in asynchronous mode"]
115    #[inline(always)]
116    pub fn x16(self) -> &'a mut W {
117        self.variant(OVS_A::X16)
118    }
119    #[doc = "Double speed with 8X oversampling in asynchronous mode"]
120    #[inline(always)]
121    pub fn x8(self) -> &'a mut W {
122        self.variant(OVS_A::X8)
123    }
124    #[doc = "6X oversampling in asynchronous mode"]
125    #[inline(always)]
126    pub fn x6(self) -> &'a mut W {
127        self.variant(OVS_A::X6)
128    }
129    #[doc = "Quadruple speed with 4X oversampling in asynchronous mode"]
130    #[inline(always)]
131    pub fn x4(self) -> &'a mut W {
132        self.variant(OVS_A::X4)
133    }
134}
135#[doc = "Field `CLKPOL` reader - Clock Polarity"]
136pub type CLKPOL_R = crate::BitReader<bool>;
137#[doc = "Field `CLKPOL` writer - Clock Polarity"]
138pub type CLKPOL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 8>;
139#[doc = "Field `CLKPHA` reader - Clock Edge For Setup/Sample"]
140pub type CLKPHA_R = crate::BitReader<bool>;
141#[doc = "Field `CLKPHA` writer - Clock Edge For Setup/Sample"]
142pub type CLKPHA_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 9>;
143#[doc = "Field `MSBF` reader - Most Significant Bit First"]
144pub type MSBF_R = crate::BitReader<bool>;
145#[doc = "Field `MSBF` writer - Most Significant Bit First"]
146pub type MSBF_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 10>;
147#[doc = "Field `CSMA` reader - Action On Slave-Select In Master Mode"]
148pub type CSMA_R = crate::BitReader<bool>;
149#[doc = "Field `CSMA` writer - Action On Slave-Select In Master Mode"]
150pub type CSMA_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 11>;
151#[doc = "Field `TXBIL` reader - TX Buffer Interrupt Level"]
152pub type TXBIL_R = crate::BitReader<bool>;
153#[doc = "Field `TXBIL` writer - TX Buffer Interrupt Level"]
154pub type TXBIL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 12>;
155#[doc = "Field `RXINV` reader - Receiver Input Invert"]
156pub type RXINV_R = crate::BitReader<bool>;
157#[doc = "Field `RXINV` writer - Receiver Input Invert"]
158pub type RXINV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 13>;
159#[doc = "Field `TXINV` reader - Transmitter output Invert"]
160pub type TXINV_R = crate::BitReader<bool>;
161#[doc = "Field `TXINV` writer - Transmitter output Invert"]
162pub type TXINV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 14>;
163#[doc = "Field `CSINV` reader - Chip Select Invert"]
164pub type CSINV_R = crate::BitReader<bool>;
165#[doc = "Field `CSINV` writer - Chip Select Invert"]
166pub type CSINV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 15>;
167#[doc = "Field `AUTOCS` reader - Automatic Chip Select"]
168pub type AUTOCS_R = crate::BitReader<bool>;
169#[doc = "Field `AUTOCS` writer - Automatic Chip Select"]
170pub type AUTOCS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 16>;
171#[doc = "Field `AUTOTRI` reader - Automatic TX Tristate"]
172pub type AUTOTRI_R = crate::BitReader<bool>;
173#[doc = "Field `AUTOTRI` writer - Automatic TX Tristate"]
174pub type AUTOTRI_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 17>;
175#[doc = "Field `SCMODE` reader - SmartCard Mode"]
176pub type SCMODE_R = crate::BitReader<bool>;
177#[doc = "Field `SCMODE` writer - SmartCard Mode"]
178pub type SCMODE_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 18>;
179#[doc = "Field `SCRETRANS` reader - SmartCard Retransmit"]
180pub type SCRETRANS_R = crate::BitReader<bool>;
181#[doc = "Field `SCRETRANS` writer - SmartCard Retransmit"]
182pub type SCRETRANS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 19>;
183#[doc = "Field `SKIPPERRF` reader - Skip Parity Error Frames"]
184pub type SKIPPERRF_R = crate::BitReader<bool>;
185#[doc = "Field `SKIPPERRF` writer - Skip Parity Error Frames"]
186pub type SKIPPERRF_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 20>;
187#[doc = "Field `BIT8DV` reader - Bit 8 Default Value"]
188pub type BIT8DV_R = crate::BitReader<bool>;
189#[doc = "Field `BIT8DV` writer - Bit 8 Default Value"]
190pub type BIT8DV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 21>;
191#[doc = "Field `ERRSDMA` reader - Halt DMA On Error"]
192pub type ERRSDMA_R = crate::BitReader<bool>;
193#[doc = "Field `ERRSDMA` writer - Halt DMA On Error"]
194pub type ERRSDMA_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 22>;
195#[doc = "Field `ERRSRX` reader - Disable RX On Error"]
196pub type ERRSRX_R = crate::BitReader<bool>;
197#[doc = "Field `ERRSRX` writer - Disable RX On Error"]
198pub type ERRSRX_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 23>;
199#[doc = "Field `ERRSTX` reader - Disable TX On Error"]
200pub type ERRSTX_R = crate::BitReader<bool>;
201#[doc = "Field `ERRSTX` writer - Disable TX On Error"]
202pub type ERRSTX_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 24>;
203#[doc = "Field `SSSEARLY` reader - Synchronous Slave Setup Early"]
204pub type SSSEARLY_R = crate::BitReader<bool>;
205#[doc = "Field `SSSEARLY` writer - Synchronous Slave Setup Early"]
206pub type SSSEARLY_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 25>;
207#[doc = "TX Delay Transmission\n\nValue on reset: 0"]
208#[derive(Clone, Copy, Debug, PartialEq)]
209#[repr(u8)]
210pub enum TXDELAY_A {
211    #[doc = "0: Frames are transmitted immediately"]
212    NONE = 0,
213    #[doc = "1: Transmission of new frames are delayed by a single baud period"]
214    SINGLE = 1,
215    #[doc = "2: Transmission of new frames are delayed by two baud periods"]
216    DOUBLE = 2,
217    #[doc = "3: Transmission of new frames are delayed by three baud periods"]
218    TRIPLE = 3,
219}
220impl From<TXDELAY_A> for u8 {
221    #[inline(always)]
222    fn from(variant: TXDELAY_A) -> Self {
223        variant as _
224    }
225}
226#[doc = "Field `TXDELAY` reader - TX Delay Transmission"]
227pub type TXDELAY_R = crate::FieldReader<u8, TXDELAY_A>;
228impl TXDELAY_R {
229    #[doc = "Get enumerated values variant"]
230    #[inline(always)]
231    pub fn variant(&self) -> TXDELAY_A {
232        match self.bits {
233            0 => TXDELAY_A::NONE,
234            1 => TXDELAY_A::SINGLE,
235            2 => TXDELAY_A::DOUBLE,
236            3 => TXDELAY_A::TRIPLE,
237            _ => unreachable!(),
238        }
239    }
240    #[doc = "Checks if the value of the field is `NONE`"]
241    #[inline(always)]
242    pub fn is_none(&self) -> bool {
243        *self == TXDELAY_A::NONE
244    }
245    #[doc = "Checks if the value of the field is `SINGLE`"]
246    #[inline(always)]
247    pub fn is_single(&self) -> bool {
248        *self == TXDELAY_A::SINGLE
249    }
250    #[doc = "Checks if the value of the field is `DOUBLE`"]
251    #[inline(always)]
252    pub fn is_double(&self) -> bool {
253        *self == TXDELAY_A::DOUBLE
254    }
255    #[doc = "Checks if the value of the field is `TRIPLE`"]
256    #[inline(always)]
257    pub fn is_triple(&self) -> bool {
258        *self == TXDELAY_A::TRIPLE
259    }
260}
261#[doc = "Field `TXDELAY` writer - TX Delay Transmission"]
262pub type TXDELAY_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, TXDELAY_A, 2, 26>;
263impl<'a> TXDELAY_W<'a> {
264    #[doc = "Frames are transmitted immediately"]
265    #[inline(always)]
266    pub fn none(self) -> &'a mut W {
267        self.variant(TXDELAY_A::NONE)
268    }
269    #[doc = "Transmission of new frames are delayed by a single baud period"]
270    #[inline(always)]
271    pub fn single(self) -> &'a mut W {
272        self.variant(TXDELAY_A::SINGLE)
273    }
274    #[doc = "Transmission of new frames are delayed by two baud periods"]
275    #[inline(always)]
276    pub fn double(self) -> &'a mut W {
277        self.variant(TXDELAY_A::DOUBLE)
278    }
279    #[doc = "Transmission of new frames are delayed by three baud periods"]
280    #[inline(always)]
281    pub fn triple(self) -> &'a mut W {
282        self.variant(TXDELAY_A::TRIPLE)
283    }
284}
285#[doc = "Field `BYTESWAP` reader - Byteswap In Double Accesses"]
286pub type BYTESWAP_R = crate::BitReader<bool>;
287#[doc = "Field `BYTESWAP` writer - Byteswap In Double Accesses"]
288pub type BYTESWAP_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 28>;
289#[doc = "Field `AUTOTX` reader - Always Transmit When RX Not Full"]
290pub type AUTOTX_R = crate::BitReader<bool>;
291#[doc = "Field `AUTOTX` writer - Always Transmit When RX Not Full"]
292pub type AUTOTX_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 29>;
293#[doc = "Field `MVDIS` reader - Majority Vote Disable"]
294pub type MVDIS_R = crate::BitReader<bool>;
295#[doc = "Field `MVDIS` writer - Majority Vote Disable"]
296pub type MVDIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 30>;
297#[doc = "Field `SMSDELAY` reader - Synchronous Master Sample Delay"]
298pub type SMSDELAY_R = crate::BitReader<bool>;
299#[doc = "Field `SMSDELAY` writer - Synchronous Master Sample Delay"]
300pub type SMSDELAY_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 31>;
301impl R {
302    #[doc = "Bit 0 - USART Synchronous Mode"]
303    #[inline(always)]
304    pub fn sync(&self) -> SYNC_R {
305        SYNC_R::new((self.bits & 1) != 0)
306    }
307    #[doc = "Bit 1 - Loopback Enable"]
308    #[inline(always)]
309    pub fn loopbk(&self) -> LOOPBK_R {
310        LOOPBK_R::new(((self.bits >> 1) & 1) != 0)
311    }
312    #[doc = "Bit 2 - Collision Check Enable"]
313    #[inline(always)]
314    pub fn ccen(&self) -> CCEN_R {
315        CCEN_R::new(((self.bits >> 2) & 1) != 0)
316    }
317    #[doc = "Bit 3 - Multi-Processor Mode"]
318    #[inline(always)]
319    pub fn mpm(&self) -> MPM_R {
320        MPM_R::new(((self.bits >> 3) & 1) != 0)
321    }
322    #[doc = "Bit 4 - Multi-Processor Address-Bit"]
323    #[inline(always)]
324    pub fn mpab(&self) -> MPAB_R {
325        MPAB_R::new(((self.bits >> 4) & 1) != 0)
326    }
327    #[doc = "Bits 5:6 - Oversampling"]
328    #[inline(always)]
329    pub fn ovs(&self) -> OVS_R {
330        OVS_R::new(((self.bits >> 5) & 3) as u8)
331    }
332    #[doc = "Bit 8 - Clock Polarity"]
333    #[inline(always)]
334    pub fn clkpol(&self) -> CLKPOL_R {
335        CLKPOL_R::new(((self.bits >> 8) & 1) != 0)
336    }
337    #[doc = "Bit 9 - Clock Edge For Setup/Sample"]
338    #[inline(always)]
339    pub fn clkpha(&self) -> CLKPHA_R {
340        CLKPHA_R::new(((self.bits >> 9) & 1) != 0)
341    }
342    #[doc = "Bit 10 - Most Significant Bit First"]
343    #[inline(always)]
344    pub fn msbf(&self) -> MSBF_R {
345        MSBF_R::new(((self.bits >> 10) & 1) != 0)
346    }
347    #[doc = "Bit 11 - Action On Slave-Select In Master Mode"]
348    #[inline(always)]
349    pub fn csma(&self) -> CSMA_R {
350        CSMA_R::new(((self.bits >> 11) & 1) != 0)
351    }
352    #[doc = "Bit 12 - TX Buffer Interrupt Level"]
353    #[inline(always)]
354    pub fn txbil(&self) -> TXBIL_R {
355        TXBIL_R::new(((self.bits >> 12) & 1) != 0)
356    }
357    #[doc = "Bit 13 - Receiver Input Invert"]
358    #[inline(always)]
359    pub fn rxinv(&self) -> RXINV_R {
360        RXINV_R::new(((self.bits >> 13) & 1) != 0)
361    }
362    #[doc = "Bit 14 - Transmitter output Invert"]
363    #[inline(always)]
364    pub fn txinv(&self) -> TXINV_R {
365        TXINV_R::new(((self.bits >> 14) & 1) != 0)
366    }
367    #[doc = "Bit 15 - Chip Select Invert"]
368    #[inline(always)]
369    pub fn csinv(&self) -> CSINV_R {
370        CSINV_R::new(((self.bits >> 15) & 1) != 0)
371    }
372    #[doc = "Bit 16 - Automatic Chip Select"]
373    #[inline(always)]
374    pub fn autocs(&self) -> AUTOCS_R {
375        AUTOCS_R::new(((self.bits >> 16) & 1) != 0)
376    }
377    #[doc = "Bit 17 - Automatic TX Tristate"]
378    #[inline(always)]
379    pub fn autotri(&self) -> AUTOTRI_R {
380        AUTOTRI_R::new(((self.bits >> 17) & 1) != 0)
381    }
382    #[doc = "Bit 18 - SmartCard Mode"]
383    #[inline(always)]
384    pub fn scmode(&self) -> SCMODE_R {
385        SCMODE_R::new(((self.bits >> 18) & 1) != 0)
386    }
387    #[doc = "Bit 19 - SmartCard Retransmit"]
388    #[inline(always)]
389    pub fn scretrans(&self) -> SCRETRANS_R {
390        SCRETRANS_R::new(((self.bits >> 19) & 1) != 0)
391    }
392    #[doc = "Bit 20 - Skip Parity Error Frames"]
393    #[inline(always)]
394    pub fn skipperrf(&self) -> SKIPPERRF_R {
395        SKIPPERRF_R::new(((self.bits >> 20) & 1) != 0)
396    }
397    #[doc = "Bit 21 - Bit 8 Default Value"]
398    #[inline(always)]
399    pub fn bit8dv(&self) -> BIT8DV_R {
400        BIT8DV_R::new(((self.bits >> 21) & 1) != 0)
401    }
402    #[doc = "Bit 22 - Halt DMA On Error"]
403    #[inline(always)]
404    pub fn errsdma(&self) -> ERRSDMA_R {
405        ERRSDMA_R::new(((self.bits >> 22) & 1) != 0)
406    }
407    #[doc = "Bit 23 - Disable RX On Error"]
408    #[inline(always)]
409    pub fn errsrx(&self) -> ERRSRX_R {
410        ERRSRX_R::new(((self.bits >> 23) & 1) != 0)
411    }
412    #[doc = "Bit 24 - Disable TX On Error"]
413    #[inline(always)]
414    pub fn errstx(&self) -> ERRSTX_R {
415        ERRSTX_R::new(((self.bits >> 24) & 1) != 0)
416    }
417    #[doc = "Bit 25 - Synchronous Slave Setup Early"]
418    #[inline(always)]
419    pub fn sssearly(&self) -> SSSEARLY_R {
420        SSSEARLY_R::new(((self.bits >> 25) & 1) != 0)
421    }
422    #[doc = "Bits 26:27 - TX Delay Transmission"]
423    #[inline(always)]
424    pub fn txdelay(&self) -> TXDELAY_R {
425        TXDELAY_R::new(((self.bits >> 26) & 3) as u8)
426    }
427    #[doc = "Bit 28 - Byteswap In Double Accesses"]
428    #[inline(always)]
429    pub fn byteswap(&self) -> BYTESWAP_R {
430        BYTESWAP_R::new(((self.bits >> 28) & 1) != 0)
431    }
432    #[doc = "Bit 29 - Always Transmit When RX Not Full"]
433    #[inline(always)]
434    pub fn autotx(&self) -> AUTOTX_R {
435        AUTOTX_R::new(((self.bits >> 29) & 1) != 0)
436    }
437    #[doc = "Bit 30 - Majority Vote Disable"]
438    #[inline(always)]
439    pub fn mvdis(&self) -> MVDIS_R {
440        MVDIS_R::new(((self.bits >> 30) & 1) != 0)
441    }
442    #[doc = "Bit 31 - Synchronous Master Sample Delay"]
443    #[inline(always)]
444    pub fn smsdelay(&self) -> SMSDELAY_R {
445        SMSDELAY_R::new(((self.bits >> 31) & 1) != 0)
446    }
447}
448impl W {
449    #[doc = "Bit 0 - USART Synchronous Mode"]
450    #[inline(always)]
451    pub fn sync(&mut self) -> SYNC_W {
452        SYNC_W::new(self)
453    }
454    #[doc = "Bit 1 - Loopback Enable"]
455    #[inline(always)]
456    pub fn loopbk(&mut self) -> LOOPBK_W {
457        LOOPBK_W::new(self)
458    }
459    #[doc = "Bit 2 - Collision Check Enable"]
460    #[inline(always)]
461    pub fn ccen(&mut self) -> CCEN_W {
462        CCEN_W::new(self)
463    }
464    #[doc = "Bit 3 - Multi-Processor Mode"]
465    #[inline(always)]
466    pub fn mpm(&mut self) -> MPM_W {
467        MPM_W::new(self)
468    }
469    #[doc = "Bit 4 - Multi-Processor Address-Bit"]
470    #[inline(always)]
471    pub fn mpab(&mut self) -> MPAB_W {
472        MPAB_W::new(self)
473    }
474    #[doc = "Bits 5:6 - Oversampling"]
475    #[inline(always)]
476    pub fn ovs(&mut self) -> OVS_W {
477        OVS_W::new(self)
478    }
479    #[doc = "Bit 8 - Clock Polarity"]
480    #[inline(always)]
481    pub fn clkpol(&mut self) -> CLKPOL_W {
482        CLKPOL_W::new(self)
483    }
484    #[doc = "Bit 9 - Clock Edge For Setup/Sample"]
485    #[inline(always)]
486    pub fn clkpha(&mut self) -> CLKPHA_W {
487        CLKPHA_W::new(self)
488    }
489    #[doc = "Bit 10 - Most Significant Bit First"]
490    #[inline(always)]
491    pub fn msbf(&mut self) -> MSBF_W {
492        MSBF_W::new(self)
493    }
494    #[doc = "Bit 11 - Action On Slave-Select In Master Mode"]
495    #[inline(always)]
496    pub fn csma(&mut self) -> CSMA_W {
497        CSMA_W::new(self)
498    }
499    #[doc = "Bit 12 - TX Buffer Interrupt Level"]
500    #[inline(always)]
501    pub fn txbil(&mut self) -> TXBIL_W {
502        TXBIL_W::new(self)
503    }
504    #[doc = "Bit 13 - Receiver Input Invert"]
505    #[inline(always)]
506    pub fn rxinv(&mut self) -> RXINV_W {
507        RXINV_W::new(self)
508    }
509    #[doc = "Bit 14 - Transmitter output Invert"]
510    #[inline(always)]
511    pub fn txinv(&mut self) -> TXINV_W {
512        TXINV_W::new(self)
513    }
514    #[doc = "Bit 15 - Chip Select Invert"]
515    #[inline(always)]
516    pub fn csinv(&mut self) -> CSINV_W {
517        CSINV_W::new(self)
518    }
519    #[doc = "Bit 16 - Automatic Chip Select"]
520    #[inline(always)]
521    pub fn autocs(&mut self) -> AUTOCS_W {
522        AUTOCS_W::new(self)
523    }
524    #[doc = "Bit 17 - Automatic TX Tristate"]
525    #[inline(always)]
526    pub fn autotri(&mut self) -> AUTOTRI_W {
527        AUTOTRI_W::new(self)
528    }
529    #[doc = "Bit 18 - SmartCard Mode"]
530    #[inline(always)]
531    pub fn scmode(&mut self) -> SCMODE_W {
532        SCMODE_W::new(self)
533    }
534    #[doc = "Bit 19 - SmartCard Retransmit"]
535    #[inline(always)]
536    pub fn scretrans(&mut self) -> SCRETRANS_W {
537        SCRETRANS_W::new(self)
538    }
539    #[doc = "Bit 20 - Skip Parity Error Frames"]
540    #[inline(always)]
541    pub fn skipperrf(&mut self) -> SKIPPERRF_W {
542        SKIPPERRF_W::new(self)
543    }
544    #[doc = "Bit 21 - Bit 8 Default Value"]
545    #[inline(always)]
546    pub fn bit8dv(&mut self) -> BIT8DV_W {
547        BIT8DV_W::new(self)
548    }
549    #[doc = "Bit 22 - Halt DMA On Error"]
550    #[inline(always)]
551    pub fn errsdma(&mut self) -> ERRSDMA_W {
552        ERRSDMA_W::new(self)
553    }
554    #[doc = "Bit 23 - Disable RX On Error"]
555    #[inline(always)]
556    pub fn errsrx(&mut self) -> ERRSRX_W {
557        ERRSRX_W::new(self)
558    }
559    #[doc = "Bit 24 - Disable TX On Error"]
560    #[inline(always)]
561    pub fn errstx(&mut self) -> ERRSTX_W {
562        ERRSTX_W::new(self)
563    }
564    #[doc = "Bit 25 - Synchronous Slave Setup Early"]
565    #[inline(always)]
566    pub fn sssearly(&mut self) -> SSSEARLY_W {
567        SSSEARLY_W::new(self)
568    }
569    #[doc = "Bits 26:27 - TX Delay Transmission"]
570    #[inline(always)]
571    pub fn txdelay(&mut self) -> TXDELAY_W {
572        TXDELAY_W::new(self)
573    }
574    #[doc = "Bit 28 - Byteswap In Double Accesses"]
575    #[inline(always)]
576    pub fn byteswap(&mut self) -> BYTESWAP_W {
577        BYTESWAP_W::new(self)
578    }
579    #[doc = "Bit 29 - Always Transmit When RX Not Full"]
580    #[inline(always)]
581    pub fn autotx(&mut self) -> AUTOTX_W {
582        AUTOTX_W::new(self)
583    }
584    #[doc = "Bit 30 - Majority Vote Disable"]
585    #[inline(always)]
586    pub fn mvdis(&mut self) -> MVDIS_W {
587        MVDIS_W::new(self)
588    }
589    #[doc = "Bit 31 - Synchronous Master Sample Delay"]
590    #[inline(always)]
591    pub fn smsdelay(&mut self) -> SMSDELAY_W {
592        SMSDELAY_W::new(self)
593    }
594    #[doc = "Writes raw bits to the register."]
595    #[inline(always)]
596    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
597        self.0.bits(bits);
598        self
599    }
600}
601#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
602pub struct CTRL_SPEC;
603impl crate::RegisterSpec for CTRL_SPEC {
604    type Ux = u32;
605}
606#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
607impl crate::Readable for CTRL_SPEC {
608    type Reader = R;
609}
610#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
611impl crate::Writable for CTRL_SPEC {
612    type Writer = W;
613}
614#[doc = "`reset()` method sets CTRL to value 0"]
615impl crate::Resettable for CTRL_SPEC {
616    #[inline(always)]
617    fn reset_value() -> Self::Ux {
618        0
619    }
620}
efm32wg230_pac/usart0/ctrl.rs

efm32wg230_pac/usart0/
ctrl.rs
