efm32wg230_pac/cmu/
hfperclken0.rs1#[doc = "Register `HFPERCLKEN0` reader"]
2pub struct R(crate::R<HFPERCLKEN0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<HFPERCLKEN0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<HFPERCLKEN0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<HFPERCLKEN0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `HFPERCLKEN0` writer"]
17pub struct W(crate::W<HFPERCLKEN0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<HFPERCLKEN0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<HFPERCLKEN0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<HFPERCLKEN0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
38pub type USART0_R = crate::BitReader<bool>;
39#[doc = "Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
40pub type USART0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 0>;
41#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
42pub type USART1_R = crate::BitReader<bool>;
43#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
44pub type USART1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 1>;
45#[doc = "Field `USART2` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
46pub type USART2_R = crate::BitReader<bool>;
47#[doc = "Field `USART2` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
48pub type USART2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 2>;
49#[doc = "Field `TIMER0` reader - Timer 0 Clock Enable"]
50pub type TIMER0_R = crate::BitReader<bool>;
51#[doc = "Field `TIMER0` writer - Timer 0 Clock Enable"]
52pub type TIMER0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 5>;
53#[doc = "Field `TIMER1` reader - Timer 1 Clock Enable"]
54pub type TIMER1_R = crate::BitReader<bool>;
55#[doc = "Field `TIMER1` writer - Timer 1 Clock Enable"]
56pub type TIMER1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 6>;
57#[doc = "Field `TIMER2` reader - Timer 2 Clock Enable"]
58pub type TIMER2_R = crate::BitReader<bool>;
59#[doc = "Field `TIMER2` writer - Timer 2 Clock Enable"]
60pub type TIMER2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 7>;
61#[doc = "Field `TIMER3` reader - Timer 3 Clock Enable"]
62pub type TIMER3_R = crate::BitReader<bool>;
63#[doc = "Field `TIMER3` writer - Timer 3 Clock Enable"]
64pub type TIMER3_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 8>;
65#[doc = "Field `ACMP0` reader - Analog Comparator 0 Clock Enable"]
66pub type ACMP0_R = crate::BitReader<bool>;
67#[doc = "Field `ACMP0` writer - Analog Comparator 0 Clock Enable"]
68pub type ACMP0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 9>;
69#[doc = "Field `ACMP1` reader - Analog Comparator 1 Clock Enable"]
70pub type ACMP1_R = crate::BitReader<bool>;
71#[doc = "Field `ACMP1` writer - Analog Comparator 1 Clock Enable"]
72pub type ACMP1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 10>;
73#[doc = "Field `I2C0` reader - I2C 0 Clock Enable"]
74pub type I2C0_R = crate::BitReader<bool>;
75#[doc = "Field `I2C0` writer - I2C 0 Clock Enable"]
76pub type I2C0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 11>;
77#[doc = "Field `I2C1` reader - I2C 1 Clock Enable"]
78pub type I2C1_R = crate::BitReader<bool>;
79#[doc = "Field `I2C1` writer - I2C 1 Clock Enable"]
80pub type I2C1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 12>;
81#[doc = "Field `GPIO` reader - General purpose Input/Output Clock Enable"]
82pub type GPIO_R = crate::BitReader<bool>;
83#[doc = "Field `GPIO` writer - General purpose Input/Output Clock Enable"]
84pub type GPIO_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 13>;
85#[doc = "Field `VCMP` reader - Voltage Comparator Clock Enable"]
86pub type VCMP_R = crate::BitReader<bool>;
87#[doc = "Field `VCMP` writer - Voltage Comparator Clock Enable"]
88pub type VCMP_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 14>;
89#[doc = "Field `PRS` reader - Peripheral Reflex System Clock Enable"]
90pub type PRS_R = crate::BitReader<bool>;
91#[doc = "Field `PRS` writer - Peripheral Reflex System Clock Enable"]
92pub type PRS_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 15>;
93#[doc = "Field `ADC0` reader - Analog to Digital Converter 0 Clock Enable"]
94pub type ADC0_R = crate::BitReader<bool>;
95#[doc = "Field `ADC0` writer - Analog to Digital Converter 0 Clock Enable"]
96pub type ADC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 16>;
97#[doc = "Field `DAC0` reader - Digital to Analog Converter 0 Clock Enable"]
98pub type DAC0_R = crate::BitReader<bool>;
99#[doc = "Field `DAC0` writer - Digital to Analog Converter 0 Clock Enable"]
100pub type DAC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 17>;
101impl R {
102 #[doc = "Bit 0 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
103 #[inline(always)]
104 pub fn usart0(&self) -> USART0_R {
105 USART0_R::new((self.bits & 1) != 0)
106 }
107 #[doc = "Bit 1 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
108 #[inline(always)]
109 pub fn usart1(&self) -> USART1_R {
110 USART1_R::new(((self.bits >> 1) & 1) != 0)
111 }
112 #[doc = "Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
113 #[inline(always)]
114 pub fn usart2(&self) -> USART2_R {
115 USART2_R::new(((self.bits >> 2) & 1) != 0)
116 }
117 #[doc = "Bit 5 - Timer 0 Clock Enable"]
118 #[inline(always)]
119 pub fn timer0(&self) -> TIMER0_R {
120 TIMER0_R::new(((self.bits >> 5) & 1) != 0)
121 }
122 #[doc = "Bit 6 - Timer 1 Clock Enable"]
123 #[inline(always)]
124 pub fn timer1(&self) -> TIMER1_R {
125 TIMER1_R::new(((self.bits >> 6) & 1) != 0)
126 }
127 #[doc = "Bit 7 - Timer 2 Clock Enable"]
128 #[inline(always)]
129 pub fn timer2(&self) -> TIMER2_R {
130 TIMER2_R::new(((self.bits >> 7) & 1) != 0)
131 }
132 #[doc = "Bit 8 - Timer 3 Clock Enable"]
133 #[inline(always)]
134 pub fn timer3(&self) -> TIMER3_R {
135 TIMER3_R::new(((self.bits >> 8) & 1) != 0)
136 }
137 #[doc = "Bit 9 - Analog Comparator 0 Clock Enable"]
138 #[inline(always)]
139 pub fn acmp0(&self) -> ACMP0_R {
140 ACMP0_R::new(((self.bits >> 9) & 1) != 0)
141 }
142 #[doc = "Bit 10 - Analog Comparator 1 Clock Enable"]
143 #[inline(always)]
144 pub fn acmp1(&self) -> ACMP1_R {
145 ACMP1_R::new(((self.bits >> 10) & 1) != 0)
146 }
147 #[doc = "Bit 11 - I2C 0 Clock Enable"]
148 #[inline(always)]
149 pub fn i2c0(&self) -> I2C0_R {
150 I2C0_R::new(((self.bits >> 11) & 1) != 0)
151 }
152 #[doc = "Bit 12 - I2C 1 Clock Enable"]
153 #[inline(always)]
154 pub fn i2c1(&self) -> I2C1_R {
155 I2C1_R::new(((self.bits >> 12) & 1) != 0)
156 }
157 #[doc = "Bit 13 - General purpose Input/Output Clock Enable"]
158 #[inline(always)]
159 pub fn gpio(&self) -> GPIO_R {
160 GPIO_R::new(((self.bits >> 13) & 1) != 0)
161 }
162 #[doc = "Bit 14 - Voltage Comparator Clock Enable"]
163 #[inline(always)]
164 pub fn vcmp(&self) -> VCMP_R {
165 VCMP_R::new(((self.bits >> 14) & 1) != 0)
166 }
167 #[doc = "Bit 15 - Peripheral Reflex System Clock Enable"]
168 #[inline(always)]
169 pub fn prs(&self) -> PRS_R {
170 PRS_R::new(((self.bits >> 15) & 1) != 0)
171 }
172 #[doc = "Bit 16 - Analog to Digital Converter 0 Clock Enable"]
173 #[inline(always)]
174 pub fn adc0(&self) -> ADC0_R {
175 ADC0_R::new(((self.bits >> 16) & 1) != 0)
176 }
177 #[doc = "Bit 17 - Digital to Analog Converter 0 Clock Enable"]
178 #[inline(always)]
179 pub fn dac0(&self) -> DAC0_R {
180 DAC0_R::new(((self.bits >> 17) & 1) != 0)
181 }
182}
183impl W {
184 #[doc = "Bit 0 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
185 #[inline(always)]
186 pub fn usart0(&mut self) -> USART0_W {
187 USART0_W::new(self)
188 }
189 #[doc = "Bit 1 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
190 #[inline(always)]
191 pub fn usart1(&mut self) -> USART1_W {
192 USART1_W::new(self)
193 }
194 #[doc = "Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
195 #[inline(always)]
196 pub fn usart2(&mut self) -> USART2_W {
197 USART2_W::new(self)
198 }
199 #[doc = "Bit 5 - Timer 0 Clock Enable"]
200 #[inline(always)]
201 pub fn timer0(&mut self) -> TIMER0_W {
202 TIMER0_W::new(self)
203 }
204 #[doc = "Bit 6 - Timer 1 Clock Enable"]
205 #[inline(always)]
206 pub fn timer1(&mut self) -> TIMER1_W {
207 TIMER1_W::new(self)
208 }
209 #[doc = "Bit 7 - Timer 2 Clock Enable"]
210 #[inline(always)]
211 pub fn timer2(&mut self) -> TIMER2_W {
212 TIMER2_W::new(self)
213 }
214 #[doc = "Bit 8 - Timer 3 Clock Enable"]
215 #[inline(always)]
216 pub fn timer3(&mut self) -> TIMER3_W {
217 TIMER3_W::new(self)
218 }
219 #[doc = "Bit 9 - Analog Comparator 0 Clock Enable"]
220 #[inline(always)]
221 pub fn acmp0(&mut self) -> ACMP0_W {
222 ACMP0_W::new(self)
223 }
224 #[doc = "Bit 10 - Analog Comparator 1 Clock Enable"]
225 #[inline(always)]
226 pub fn acmp1(&mut self) -> ACMP1_W {
227 ACMP1_W::new(self)
228 }
229 #[doc = "Bit 11 - I2C 0 Clock Enable"]
230 #[inline(always)]
231 pub fn i2c0(&mut self) -> I2C0_W {
232 I2C0_W::new(self)
233 }
234 #[doc = "Bit 12 - I2C 1 Clock Enable"]
235 #[inline(always)]
236 pub fn i2c1(&mut self) -> I2C1_W {
237 I2C1_W::new(self)
238 }
239 #[doc = "Bit 13 - General purpose Input/Output Clock Enable"]
240 #[inline(always)]
241 pub fn gpio(&mut self) -> GPIO_W {
242 GPIO_W::new(self)
243 }
244 #[doc = "Bit 14 - Voltage Comparator Clock Enable"]
245 #[inline(always)]
246 pub fn vcmp(&mut self) -> VCMP_W {
247 VCMP_W::new(self)
248 }
249 #[doc = "Bit 15 - Peripheral Reflex System Clock Enable"]
250 #[inline(always)]
251 pub fn prs(&mut self) -> PRS_W {
252 PRS_W::new(self)
253 }
254 #[doc = "Bit 16 - Analog to Digital Converter 0 Clock Enable"]
255 #[inline(always)]
256 pub fn adc0(&mut self) -> ADC0_W {
257 ADC0_W::new(self)
258 }
259 #[doc = "Bit 17 - Digital to Analog Converter 0 Clock Enable"]
260 #[inline(always)]
261 pub fn dac0(&mut self) -> DAC0_W {
262 DAC0_W::new(self)
263 }
264 #[doc = "Writes raw bits to the register."]
265 #[inline(always)]
266 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
267 self.0.bits(bits);
268 self
269 }
270}
271#[doc = "High Frequency Peripheral Clock Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfperclken0](index.html) module"]
272pub struct HFPERCLKEN0_SPEC;
273impl crate::RegisterSpec for HFPERCLKEN0_SPEC {
274 type Ux = u32;
275}
276#[doc = "`read()` method returns [hfperclken0::R](R) reader structure"]
277impl crate::Readable for HFPERCLKEN0_SPEC {
278 type Reader = R;
279}
280#[doc = "`write(|w| ..)` method takes [hfperclken0::W](W) writer structure"]
281impl crate::Writable for HFPERCLKEN0_SPEC {
282 type Writer = W;
283}
284#[doc = "`reset()` method sets HFPERCLKEN0 to value 0"]
285impl crate::Resettable for HFPERCLKEN0_SPEC {
286 #[inline(always)]
287 fn reset_value() -> Self::Ux {
288 0
289 }
290}