efm32wg230_pac/dma/
chens.rs

1#[doc = "Register `CHENS` writer"]
2pub struct W(crate::W<CHENS_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CHENS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CHENS_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CHENS_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `CH0ENS` writer - Channel 0 Enable Set"]
23pub type CH0ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 0>;
24#[doc = "Field `CH1ENS` writer - Channel 1 Enable Set"]
25pub type CH1ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 1>;
26#[doc = "Field `CH2ENS` writer - Channel 2 Enable Set"]
27pub type CH2ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 2>;
28#[doc = "Field `CH3ENS` writer - Channel 3 Enable Set"]
29pub type CH3ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 3>;
30#[doc = "Field `CH4ENS` writer - Channel 4 Enable Set"]
31pub type CH4ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 4>;
32#[doc = "Field `CH5ENS` writer - Channel 5 Enable Set"]
33pub type CH5ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 5>;
34#[doc = "Field `CH6ENS` writer - Channel 6 Enable Set"]
35pub type CH6ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 6>;
36#[doc = "Field `CH7ENS` writer - Channel 7 Enable Set"]
37pub type CH7ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 7>;
38#[doc = "Field `CH8ENS` writer - Channel 8 Enable Set"]
39pub type CH8ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 8>;
40#[doc = "Field `CH9ENS` writer - Channel 9 Enable Set"]
41pub type CH9ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 9>;
42#[doc = "Field `CH10ENS` writer - Channel 10 Enable Set"]
43pub type CH10ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 10>;
44#[doc = "Field `CH11ENS` writer - Channel 11 Enable Set"]
45pub type CH11ENS_W<'a> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, 11>;
46impl W {
47    #[doc = "Bit 0 - Channel 0 Enable Set"]
48    #[inline(always)]
49    pub fn ch0ens(&mut self) -> CH0ENS_W {
50        CH0ENS_W::new(self)
51    }
52    #[doc = "Bit 1 - Channel 1 Enable Set"]
53    #[inline(always)]
54    pub fn ch1ens(&mut self) -> CH1ENS_W {
55        CH1ENS_W::new(self)
56    }
57    #[doc = "Bit 2 - Channel 2 Enable Set"]
58    #[inline(always)]
59    pub fn ch2ens(&mut self) -> CH2ENS_W {
60        CH2ENS_W::new(self)
61    }
62    #[doc = "Bit 3 - Channel 3 Enable Set"]
63    #[inline(always)]
64    pub fn ch3ens(&mut self) -> CH3ENS_W {
65        CH3ENS_W::new(self)
66    }
67    #[doc = "Bit 4 - Channel 4 Enable Set"]
68    #[inline(always)]
69    pub fn ch4ens(&mut self) -> CH4ENS_W {
70        CH4ENS_W::new(self)
71    }
72    #[doc = "Bit 5 - Channel 5 Enable Set"]
73    #[inline(always)]
74    pub fn ch5ens(&mut self) -> CH5ENS_W {
75        CH5ENS_W::new(self)
76    }
77    #[doc = "Bit 6 - Channel 6 Enable Set"]
78    #[inline(always)]
79    pub fn ch6ens(&mut self) -> CH6ENS_W {
80        CH6ENS_W::new(self)
81    }
82    #[doc = "Bit 7 - Channel 7 Enable Set"]
83    #[inline(always)]
84    pub fn ch7ens(&mut self) -> CH7ENS_W {
85        CH7ENS_W::new(self)
86    }
87    #[doc = "Bit 8 - Channel 8 Enable Set"]
88    #[inline(always)]
89    pub fn ch8ens(&mut self) -> CH8ENS_W {
90        CH8ENS_W::new(self)
91    }
92    #[doc = "Bit 9 - Channel 9 Enable Set"]
93    #[inline(always)]
94    pub fn ch9ens(&mut self) -> CH9ENS_W {
95        CH9ENS_W::new(self)
96    }
97    #[doc = "Bit 10 - Channel 10 Enable Set"]
98    #[inline(always)]
99    pub fn ch10ens(&mut self) -> CH10ENS_W {
100        CH10ENS_W::new(self)
101    }
102    #[doc = "Bit 11 - Channel 11 Enable Set"]
103    #[inline(always)]
104    pub fn ch11ens(&mut self) -> CH11ENS_W {
105        CH11ENS_W::new(self)
106    }
107    #[doc = "Writes raw bits to the register."]
108    #[inline(always)]
109    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
110        self.0.bits(bits);
111        self
112    }
113}
114#[doc = "Channel Enable Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chens](index.html) module"]
115pub struct CHENS_SPEC;
116impl crate::RegisterSpec for CHENS_SPEC {
117    type Ux = u32;
118}
119#[doc = "`write(|w| ..)` method takes [chens::W](W) writer structure"]
120impl crate::Writable for CHENS_SPEC {
121    type Writer = W;
122}
123#[doc = "`reset()` method sets CHENS to value 0"]
124impl crate::Resettable for CHENS_SPEC {
125    #[inline(always)]
126    fn reset_value() -> Self::Ux {
127        0
128    }
129}
efm32wg230_pac/dma/chens.rs

efm32wg230_pac/dma/
chens.rs
