efm32wg230_pac/prs/
ch7_ctrl.rs

1#[doc = "Register `CH7_CTRL` reader"]
2pub struct R(crate::R<CH7_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH7_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH7_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH7_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH7_CTRL` writer"]
17pub struct W(crate::W<CH7_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH7_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH7_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH7_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH7_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Voltage Comparator"]
48    VCMP = 1,
49    #[doc = "2: Analog Comparator 0"]
50    ACMP0 = 2,
51    #[doc = "3: Analog Comparator 1"]
52    ACMP1 = 3,
53    #[doc = "6: Digital to Analog Converter 0"]
54    DAC0 = 6,
55    #[doc = "8: Analog to Digital Converter 0"]
56    ADC0 = 8,
57    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
58    USART0 = 16,
59    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
60    USART1 = 17,
61    #[doc = "18: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
62    USART2 = 18,
63    #[doc = "28: Timer 0"]
64    TIMER0 = 28,
65    #[doc = "29: Timer 1"]
66    TIMER1 = 29,
67    #[doc = "30: Timer 2"]
68    TIMER2 = 30,
69    #[doc = "31: Timer 3"]
70    TIMER3 = 31,
71    #[doc = "40: Real-Time Counter"]
72    RTC = 40,
73    #[doc = "48: General purpose Input/Output"]
74    GPIOL = 48,
75    #[doc = "49: General purpose Input/Output"]
76    GPIOH = 49,
77    #[doc = "52: Low Energy Timer 0"]
78    LETIMER0 = 52,
79    #[doc = "55: Backup RTC"]
80    BURTC = 55,
81    #[doc = "57: Low Energy Sensor Interface"]
82    LESENSEL = 57,
83    #[doc = "58: Low Energy Sensor Interface"]
84    LESENSEH = 58,
85    #[doc = "59: Low Energy Sensor Interface"]
86    LESENSED = 59,
87}
88impl From<SOURCESEL_A> for u8 {
89    #[inline(always)]
90    fn from(variant: SOURCESEL_A) -> Self {
91        variant as _
92    }
93}
94#[doc = "Field `SOURCESEL` reader - Source Select"]
95pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
96impl SOURCESEL_R {
97    #[doc = "Get enumerated values variant"]
98    #[inline(always)]
99    pub fn variant(&self) -> Option<SOURCESEL_A> {
100        match self.bits {
101            0 => Some(SOURCESEL_A::NONE),
102            1 => Some(SOURCESEL_A::VCMP),
103            2 => Some(SOURCESEL_A::ACMP0),
104            3 => Some(SOURCESEL_A::ACMP1),
105            6 => Some(SOURCESEL_A::DAC0),
106            8 => Some(SOURCESEL_A::ADC0),
107            16 => Some(SOURCESEL_A::USART0),
108            17 => Some(SOURCESEL_A::USART1),
109            18 => Some(SOURCESEL_A::USART2),
110            28 => Some(SOURCESEL_A::TIMER0),
111            29 => Some(SOURCESEL_A::TIMER1),
112            30 => Some(SOURCESEL_A::TIMER2),
113            31 => Some(SOURCESEL_A::TIMER3),
114            40 => Some(SOURCESEL_A::RTC),
115            48 => Some(SOURCESEL_A::GPIOL),
116            49 => Some(SOURCESEL_A::GPIOH),
117            52 => Some(SOURCESEL_A::LETIMER0),
118            55 => Some(SOURCESEL_A::BURTC),
119            57 => Some(SOURCESEL_A::LESENSEL),
120            58 => Some(SOURCESEL_A::LESENSEH),
121            59 => Some(SOURCESEL_A::LESENSED),
122            _ => None,
123        }
124    }
125    #[doc = "Checks if the value of the field is `NONE`"]
126    #[inline(always)]
127    pub fn is_none(&self) -> bool {
128        *self == SOURCESEL_A::NONE
129    }
130    #[doc = "Checks if the value of the field is `VCMP`"]
131    #[inline(always)]
132    pub fn is_vcmp(&self) -> bool {
133        *self == SOURCESEL_A::VCMP
134    }
135    #[doc = "Checks if the value of the field is `ACMP0`"]
136    #[inline(always)]
137    pub fn is_acmp0(&self) -> bool {
138        *self == SOURCESEL_A::ACMP0
139    }
140    #[doc = "Checks if the value of the field is `ACMP1`"]
141    #[inline(always)]
142    pub fn is_acmp1(&self) -> bool {
143        *self == SOURCESEL_A::ACMP1
144    }
145    #[doc = "Checks if the value of the field is `DAC0`"]
146    #[inline(always)]
147    pub fn is_dac0(&self) -> bool {
148        *self == SOURCESEL_A::DAC0
149    }
150    #[doc = "Checks if the value of the field is `ADC0`"]
151    #[inline(always)]
152    pub fn is_adc0(&self) -> bool {
153        *self == SOURCESEL_A::ADC0
154    }
155    #[doc = "Checks if the value of the field is `USART0`"]
156    #[inline(always)]
157    pub fn is_usart0(&self) -> bool {
158        *self == SOURCESEL_A::USART0
159    }
160    #[doc = "Checks if the value of the field is `USART1`"]
161    #[inline(always)]
162    pub fn is_usart1(&self) -> bool {
163        *self == SOURCESEL_A::USART1
164    }
165    #[doc = "Checks if the value of the field is `USART2`"]
166    #[inline(always)]
167    pub fn is_usart2(&self) -> bool {
168        *self == SOURCESEL_A::USART2
169    }
170    #[doc = "Checks if the value of the field is `TIMER0`"]
171    #[inline(always)]
172    pub fn is_timer0(&self) -> bool {
173        *self == SOURCESEL_A::TIMER0
174    }
175    #[doc = "Checks if the value of the field is `TIMER1`"]
176    #[inline(always)]
177    pub fn is_timer1(&self) -> bool {
178        *self == SOURCESEL_A::TIMER1
179    }
180    #[doc = "Checks if the value of the field is `TIMER2`"]
181    #[inline(always)]
182    pub fn is_timer2(&self) -> bool {
183        *self == SOURCESEL_A::TIMER2
184    }
185    #[doc = "Checks if the value of the field is `TIMER3`"]
186    #[inline(always)]
187    pub fn is_timer3(&self) -> bool {
188        *self == SOURCESEL_A::TIMER3
189    }
190    #[doc = "Checks if the value of the field is `RTC`"]
191    #[inline(always)]
192    pub fn is_rtc(&self) -> bool {
193        *self == SOURCESEL_A::RTC
194    }
195    #[doc = "Checks if the value of the field is `GPIOL`"]
196    #[inline(always)]
197    pub fn is_gpiol(&self) -> bool {
198        *self == SOURCESEL_A::GPIOL
199    }
200    #[doc = "Checks if the value of the field is `GPIOH`"]
201    #[inline(always)]
202    pub fn is_gpioh(&self) -> bool {
203        *self == SOURCESEL_A::GPIOH
204    }
205    #[doc = "Checks if the value of the field is `LETIMER0`"]
206    #[inline(always)]
207    pub fn is_letimer0(&self) -> bool {
208        *self == SOURCESEL_A::LETIMER0
209    }
210    #[doc = "Checks if the value of the field is `BURTC`"]
211    #[inline(always)]
212    pub fn is_burtc(&self) -> bool {
213        *self == SOURCESEL_A::BURTC
214    }
215    #[doc = "Checks if the value of the field is `LESENSEL`"]
216    #[inline(always)]
217    pub fn is_lesensel(&self) -> bool {
218        *self == SOURCESEL_A::LESENSEL
219    }
220    #[doc = "Checks if the value of the field is `LESENSEH`"]
221    #[inline(always)]
222    pub fn is_lesenseh(&self) -> bool {
223        *self == SOURCESEL_A::LESENSEH
224    }
225    #[doc = "Checks if the value of the field is `LESENSED`"]
226    #[inline(always)]
227    pub fn is_lesensed(&self) -> bool {
228        *self == SOURCESEL_A::LESENSED
229    }
230}
231#[doc = "Field `SOURCESEL` writer - Source Select"]
232pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH7_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
233impl<'a> SOURCESEL_W<'a> {
234    #[doc = "No source selected"]
235    #[inline(always)]
236    pub fn none(self) -> &'a mut W {
237        self.variant(SOURCESEL_A::NONE)
238    }
239    #[doc = "Voltage Comparator"]
240    #[inline(always)]
241    pub fn vcmp(self) -> &'a mut W {
242        self.variant(SOURCESEL_A::VCMP)
243    }
244    #[doc = "Analog Comparator 0"]
245    #[inline(always)]
246    pub fn acmp0(self) -> &'a mut W {
247        self.variant(SOURCESEL_A::ACMP0)
248    }
249    #[doc = "Analog Comparator 1"]
250    #[inline(always)]
251    pub fn acmp1(self) -> &'a mut W {
252        self.variant(SOURCESEL_A::ACMP1)
253    }
254    #[doc = "Digital to Analog Converter 0"]
255    #[inline(always)]
256    pub fn dac0(self) -> &'a mut W {
257        self.variant(SOURCESEL_A::DAC0)
258    }
259    #[doc = "Analog to Digital Converter 0"]
260    #[inline(always)]
261    pub fn adc0(self) -> &'a mut W {
262        self.variant(SOURCESEL_A::ADC0)
263    }
264    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
265    #[inline(always)]
266    pub fn usart0(self) -> &'a mut W {
267        self.variant(SOURCESEL_A::USART0)
268    }
269    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
270    #[inline(always)]
271    pub fn usart1(self) -> &'a mut W {
272        self.variant(SOURCESEL_A::USART1)
273    }
274    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
275    #[inline(always)]
276    pub fn usart2(self) -> &'a mut W {
277        self.variant(SOURCESEL_A::USART2)
278    }
279    #[doc = "Timer 0"]
280    #[inline(always)]
281    pub fn timer0(self) -> &'a mut W {
282        self.variant(SOURCESEL_A::TIMER0)
283    }
284    #[doc = "Timer 1"]
285    #[inline(always)]
286    pub fn timer1(self) -> &'a mut W {
287        self.variant(SOURCESEL_A::TIMER1)
288    }
289    #[doc = "Timer 2"]
290    #[inline(always)]
291    pub fn timer2(self) -> &'a mut W {
292        self.variant(SOURCESEL_A::TIMER2)
293    }
294    #[doc = "Timer 3"]
295    #[inline(always)]
296    pub fn timer3(self) -> &'a mut W {
297        self.variant(SOURCESEL_A::TIMER3)
298    }
299    #[doc = "Real-Time Counter"]
300    #[inline(always)]
301    pub fn rtc(self) -> &'a mut W {
302        self.variant(SOURCESEL_A::RTC)
303    }
304    #[doc = "General purpose Input/Output"]
305    #[inline(always)]
306    pub fn gpiol(self) -> &'a mut W {
307        self.variant(SOURCESEL_A::GPIOL)
308    }
309    #[doc = "General purpose Input/Output"]
310    #[inline(always)]
311    pub fn gpioh(self) -> &'a mut W {
312        self.variant(SOURCESEL_A::GPIOH)
313    }
314    #[doc = "Low Energy Timer 0"]
315    #[inline(always)]
316    pub fn letimer0(self) -> &'a mut W {
317        self.variant(SOURCESEL_A::LETIMER0)
318    }
319    #[doc = "Backup RTC"]
320    #[inline(always)]
321    pub fn burtc(self) -> &'a mut W {
322        self.variant(SOURCESEL_A::BURTC)
323    }
324    #[doc = "Low Energy Sensor Interface"]
325    #[inline(always)]
326    pub fn lesensel(self) -> &'a mut W {
327        self.variant(SOURCESEL_A::LESENSEL)
328    }
329    #[doc = "Low Energy Sensor Interface"]
330    #[inline(always)]
331    pub fn lesenseh(self) -> &'a mut W {
332        self.variant(SOURCESEL_A::LESENSEH)
333    }
334    #[doc = "Low Energy Sensor Interface"]
335    #[inline(always)]
336    pub fn lesensed(self) -> &'a mut W {
337        self.variant(SOURCESEL_A::LESENSED)
338    }
339}
340#[doc = "Edge Detect Select\n\nValue on reset: 0"]
341#[derive(Clone, Copy, Debug, PartialEq)]
342#[repr(u8)]
343pub enum EDSEL_A {
344    #[doc = "0: Signal is left as it is"]
345    OFF = 0,
346    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
347    POSEDGE = 1,
348    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
349    NEGEDGE = 2,
350    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
351    BOTHEDGES = 3,
352}
353impl From<EDSEL_A> for u8 {
354    #[inline(always)]
355    fn from(variant: EDSEL_A) -> Self {
356        variant as _
357    }
358}
359#[doc = "Field `EDSEL` reader - Edge Detect Select"]
360pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
361impl EDSEL_R {
362    #[doc = "Get enumerated values variant"]
363    #[inline(always)]
364    pub fn variant(&self) -> EDSEL_A {
365        match self.bits {
366            0 => EDSEL_A::OFF,
367            1 => EDSEL_A::POSEDGE,
368            2 => EDSEL_A::NEGEDGE,
369            3 => EDSEL_A::BOTHEDGES,
370            _ => unreachable!(),
371        }
372    }
373    #[doc = "Checks if the value of the field is `OFF`"]
374    #[inline(always)]
375    pub fn is_off(&self) -> bool {
376        *self == EDSEL_A::OFF
377    }
378    #[doc = "Checks if the value of the field is `POSEDGE`"]
379    #[inline(always)]
380    pub fn is_posedge(&self) -> bool {
381        *self == EDSEL_A::POSEDGE
382    }
383    #[doc = "Checks if the value of the field is `NEGEDGE`"]
384    #[inline(always)]
385    pub fn is_negedge(&self) -> bool {
386        *self == EDSEL_A::NEGEDGE
387    }
388    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
389    #[inline(always)]
390    pub fn is_bothedges(&self) -> bool {
391        *self == EDSEL_A::BOTHEDGES
392    }
393}
394#[doc = "Field `EDSEL` writer - Edge Detect Select"]
395pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH7_CTRL_SPEC, u8, EDSEL_A, 2, 24>;
396impl<'a> EDSEL_W<'a> {
397    #[doc = "Signal is left as it is"]
398    #[inline(always)]
399    pub fn off(self) -> &'a mut W {
400        self.variant(EDSEL_A::OFF)
401    }
402    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
403    #[inline(always)]
404    pub fn posedge(self) -> &'a mut W {
405        self.variant(EDSEL_A::POSEDGE)
406    }
407    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
408    #[inline(always)]
409    pub fn negedge(self) -> &'a mut W {
410        self.variant(EDSEL_A::NEGEDGE)
411    }
412    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
413    #[inline(always)]
414    pub fn bothedges(self) -> &'a mut W {
415        self.variant(EDSEL_A::BOTHEDGES)
416    }
417}
418#[doc = "Field `ASYNC` reader - Asynchronous reflex"]
419pub type ASYNC_R = crate::BitReader<bool>;
420#[doc = "Field `ASYNC` writer - Asynchronous reflex"]
421pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, 28>;
422impl R {
423    #[doc = "Bits 0:2 - Signal Select"]
424    #[inline(always)]
425    pub fn sigsel(&self) -> SIGSEL_R {
426        SIGSEL_R::new((self.bits & 7) as u8)
427    }
428    #[doc = "Bits 16:21 - Source Select"]
429    #[inline(always)]
430    pub fn sourcesel(&self) -> SOURCESEL_R {
431        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
432    }
433    #[doc = "Bits 24:25 - Edge Detect Select"]
434    #[inline(always)]
435    pub fn edsel(&self) -> EDSEL_R {
436        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
437    }
438    #[doc = "Bit 28 - Asynchronous reflex"]
439    #[inline(always)]
440    pub fn async_(&self) -> ASYNC_R {
441        ASYNC_R::new(((self.bits >> 28) & 1) != 0)
442    }
443}
444impl W {
445    #[doc = "Bits 0:2 - Signal Select"]
446    #[inline(always)]
447    pub fn sigsel(&mut self) -> SIGSEL_W {
448        SIGSEL_W::new(self)
449    }
450    #[doc = "Bits 16:21 - Source Select"]
451    #[inline(always)]
452    pub fn sourcesel(&mut self) -> SOURCESEL_W {
453        SOURCESEL_W::new(self)
454    }
455    #[doc = "Bits 24:25 - Edge Detect Select"]
456    #[inline(always)]
457    pub fn edsel(&mut self) -> EDSEL_W {
458        EDSEL_W::new(self)
459    }
460    #[doc = "Bit 28 - Asynchronous reflex"]
461    #[inline(always)]
462    pub fn async_(&mut self) -> ASYNC_W {
463        ASYNC_W::new(self)
464    }
465    #[doc = "Writes raw bits to the register."]
466    #[inline(always)]
467    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
468        self.0.bits(bits);
469        self
470    }
471}
472#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch7_ctrl](index.html) module"]
473pub struct CH7_CTRL_SPEC;
474impl crate::RegisterSpec for CH7_CTRL_SPEC {
475    type Ux = u32;
476}
477#[doc = "`read()` method returns [ch7_ctrl::R](R) reader structure"]
478impl crate::Readable for CH7_CTRL_SPEC {
479    type Reader = R;
480}
481#[doc = "`write(|w| ..)` method takes [ch7_ctrl::W](W) writer structure"]
482impl crate::Writable for CH7_CTRL_SPEC {
483    type Writer = W;
484}
485#[doc = "`reset()` method sets CH7_CTRL to value 0"]
486impl crate::Resettable for CH7_CTRL_SPEC {
487    #[inline(always)]
488    fn reset_value() -> Self::Ux {
489        0
490    }
491}
efm32wg230_pac/prs/ch7_ctrl.rs

efm32wg230_pac/prs/
ch7_ctrl.rs
