1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Mode Select\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum MODE_A {
41 #[doc = "0: The module is disabled."]
42 DISABLE = 0,
43 #[doc = "1: Single input LFACLK oversampling mode (available in EM0-EM2)."]
44 OVSSINGLE = 1,
45 #[doc = "2: Externally clocked single input counter mode (available in EM0-EM3)."]
46 EXTCLKSINGLE = 2,
47 #[doc = "3: Externally clocked quadrature decoder mode (available in EM0-EM3)."]
48 EXTCLKQUAD = 3,
49}
50impl From<MODE_A> for u8 {
51 #[inline(always)]
52 fn from(variant: MODE_A) -> Self {
53 variant as _
54 }
55}
56#[doc = "Field `MODE` reader - Mode Select"]
57pub type MODE_R = crate::FieldReader<u8, MODE_A>;
58impl MODE_R {
59 #[doc = "Get enumerated values variant"]
60 #[inline(always)]
61 pub fn variant(&self) -> MODE_A {
62 match self.bits {
63 0 => MODE_A::DISABLE,
64 1 => MODE_A::OVSSINGLE,
65 2 => MODE_A::EXTCLKSINGLE,
66 3 => MODE_A::EXTCLKQUAD,
67 _ => unreachable!(),
68 }
69 }
70 #[doc = "Checks if the value of the field is `DISABLE`"]
71 #[inline(always)]
72 pub fn is_disable(&self) -> bool {
73 *self == MODE_A::DISABLE
74 }
75 #[doc = "Checks if the value of the field is `OVSSINGLE`"]
76 #[inline(always)]
77 pub fn is_ovssingle(&self) -> bool {
78 *self == MODE_A::OVSSINGLE
79 }
80 #[doc = "Checks if the value of the field is `EXTCLKSINGLE`"]
81 #[inline(always)]
82 pub fn is_extclksingle(&self) -> bool {
83 *self == MODE_A::EXTCLKSINGLE
84 }
85 #[doc = "Checks if the value of the field is `EXTCLKQUAD`"]
86 #[inline(always)]
87 pub fn is_extclkquad(&self) -> bool {
88 *self == MODE_A::EXTCLKQUAD
89 }
90}
91#[doc = "Field `MODE` writer - Mode Select"]
92pub type MODE_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, MODE_A, 2, 0>;
93impl<'a> MODE_W<'a> {
94 #[doc = "The module is disabled."]
95 #[inline(always)]
96 pub fn disable(self) -> &'a mut W {
97 self.variant(MODE_A::DISABLE)
98 }
99 #[doc = "Single input LFACLK oversampling mode (available in EM0-EM2)."]
100 #[inline(always)]
101 pub fn ovssingle(self) -> &'a mut W {
102 self.variant(MODE_A::OVSSINGLE)
103 }
104 #[doc = "Externally clocked single input counter mode (available in EM0-EM3)."]
105 #[inline(always)]
106 pub fn extclksingle(self) -> &'a mut W {
107 self.variant(MODE_A::EXTCLKSINGLE)
108 }
109 #[doc = "Externally clocked quadrature decoder mode (available in EM0-EM3)."]
110 #[inline(always)]
111 pub fn extclkquad(self) -> &'a mut W {
112 self.variant(MODE_A::EXTCLKQUAD)
113 }
114}
115#[doc = "Field `CNTDIR` reader - Non-Quadrature Mode Counter Direction Control"]
116pub type CNTDIR_R = crate::BitReader<bool>;
117#[doc = "Field `CNTDIR` writer - Non-Quadrature Mode Counter Direction Control"]
118pub type CNTDIR_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 2>;
119#[doc = "Field `EDGE` reader - Edge Select"]
120pub type EDGE_R = crate::BitReader<bool>;
121#[doc = "Field `EDGE` writer - Edge Select"]
122pub type EDGE_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 3>;
123#[doc = "Field `FILT` reader - Enable Digital Pulse Width Filter"]
124pub type FILT_R = crate::BitReader<bool>;
125#[doc = "Field `FILT` writer - Enable Digital Pulse Width Filter"]
126pub type FILT_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 4>;
127#[doc = "Field `RSTEN` reader - Enable PCNT Clock Domain Reset"]
128pub type RSTEN_R = crate::BitReader<bool>;
129#[doc = "Field `RSTEN` writer - Enable PCNT Clock Domain Reset"]
130pub type RSTEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 5>;
131#[doc = "Field `HYST` reader - Enable Hysteresis"]
132pub type HYST_R = crate::BitReader<bool>;
133#[doc = "Field `HYST` writer - Enable Hysteresis"]
134pub type HYST_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 8>;
135#[doc = "Field `S1CDIR` reader - Count direction determined by S1"]
136pub type S1CDIR_R = crate::BitReader<bool>;
137#[doc = "Field `S1CDIR` writer - Count direction determined by S1"]
138pub type S1CDIR_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 9>;
139#[doc = "Controls when the counter counts\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141#[repr(u8)]
142pub enum CNTEV_A {
143 #[doc = "0: Counts up on up-count and down on down-count events."]
144 BOTH = 0,
145 #[doc = "1: Only counts up on up-count events."]
146 UP = 1,
147 #[doc = "2: Only counts down on down-count events."]
148 DOWN = 2,
149 #[doc = "3: Never counts."]
150 NONE = 3,
151}
152impl From<CNTEV_A> for u8 {
153 #[inline(always)]
154 fn from(variant: CNTEV_A) -> Self {
155 variant as _
156 }
157}
158#[doc = "Field `CNTEV` reader - Controls when the counter counts"]
159pub type CNTEV_R = crate::FieldReader<u8, CNTEV_A>;
160impl CNTEV_R {
161 #[doc = "Get enumerated values variant"]
162 #[inline(always)]
163 pub fn variant(&self) -> CNTEV_A {
164 match self.bits {
165 0 => CNTEV_A::BOTH,
166 1 => CNTEV_A::UP,
167 2 => CNTEV_A::DOWN,
168 3 => CNTEV_A::NONE,
169 _ => unreachable!(),
170 }
171 }
172 #[doc = "Checks if the value of the field is `BOTH`"]
173 #[inline(always)]
174 pub fn is_both(&self) -> bool {
175 *self == CNTEV_A::BOTH
176 }
177 #[doc = "Checks if the value of the field is `UP`"]
178 #[inline(always)]
179 pub fn is_up(&self) -> bool {
180 *self == CNTEV_A::UP
181 }
182 #[doc = "Checks if the value of the field is `DOWN`"]
183 #[inline(always)]
184 pub fn is_down(&self) -> bool {
185 *self == CNTEV_A::DOWN
186 }
187 #[doc = "Checks if the value of the field is `NONE`"]
188 #[inline(always)]
189 pub fn is_none(&self) -> bool {
190 *self == CNTEV_A::NONE
191 }
192}
193#[doc = "Field `CNTEV` writer - Controls when the counter counts"]
194pub type CNTEV_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, CNTEV_A, 2, 10>;
195impl<'a> CNTEV_W<'a> {
196 #[doc = "Counts up on up-count and down on down-count events."]
197 #[inline(always)]
198 pub fn both(self) -> &'a mut W {
199 self.variant(CNTEV_A::BOTH)
200 }
201 #[doc = "Only counts up on up-count events."]
202 #[inline(always)]
203 pub fn up(self) -> &'a mut W {
204 self.variant(CNTEV_A::UP)
205 }
206 #[doc = "Only counts down on down-count events."]
207 #[inline(always)]
208 pub fn down(self) -> &'a mut W {
209 self.variant(CNTEV_A::DOWN)
210 }
211 #[doc = "Never counts."]
212 #[inline(always)]
213 pub fn none(self) -> &'a mut W {
214 self.variant(CNTEV_A::NONE)
215 }
216}
217#[doc = "Controls when the auxiliary counter counts\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq)]
219#[repr(u8)]
220pub enum AUXCNTEV_A {
221 #[doc = "0: Never counts."]
222 NONE = 0,
223 #[doc = "1: Counts up on up-count events."]
224 UP = 1,
225 #[doc = "2: Counts up on down-count events."]
226 DOWN = 2,
227 #[doc = "3: Counts up on both up-count and down-count events."]
228 BOTH = 3,
229}
230impl From<AUXCNTEV_A> for u8 {
231 #[inline(always)]
232 fn from(variant: AUXCNTEV_A) -> Self {
233 variant as _
234 }
235}
236#[doc = "Field `AUXCNTEV` reader - Controls when the auxiliary counter counts"]
237pub type AUXCNTEV_R = crate::FieldReader<u8, AUXCNTEV_A>;
238impl AUXCNTEV_R {
239 #[doc = "Get enumerated values variant"]
240 #[inline(always)]
241 pub fn variant(&self) -> AUXCNTEV_A {
242 match self.bits {
243 0 => AUXCNTEV_A::NONE,
244 1 => AUXCNTEV_A::UP,
245 2 => AUXCNTEV_A::DOWN,
246 3 => AUXCNTEV_A::BOTH,
247 _ => unreachable!(),
248 }
249 }
250 #[doc = "Checks if the value of the field is `NONE`"]
251 #[inline(always)]
252 pub fn is_none(&self) -> bool {
253 *self == AUXCNTEV_A::NONE
254 }
255 #[doc = "Checks if the value of the field is `UP`"]
256 #[inline(always)]
257 pub fn is_up(&self) -> bool {
258 *self == AUXCNTEV_A::UP
259 }
260 #[doc = "Checks if the value of the field is `DOWN`"]
261 #[inline(always)]
262 pub fn is_down(&self) -> bool {
263 *self == AUXCNTEV_A::DOWN
264 }
265 #[doc = "Checks if the value of the field is `BOTH`"]
266 #[inline(always)]
267 pub fn is_both(&self) -> bool {
268 *self == AUXCNTEV_A::BOTH
269 }
270}
271#[doc = "Field `AUXCNTEV` writer - Controls when the auxiliary counter counts"]
272pub type AUXCNTEV_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, AUXCNTEV_A, 2, 14>;
273impl<'a> AUXCNTEV_W<'a> {
274 #[doc = "Never counts."]
275 #[inline(always)]
276 pub fn none(self) -> &'a mut W {
277 self.variant(AUXCNTEV_A::NONE)
278 }
279 #[doc = "Counts up on up-count events."]
280 #[inline(always)]
281 pub fn up(self) -> &'a mut W {
282 self.variant(AUXCNTEV_A::UP)
283 }
284 #[doc = "Counts up on down-count events."]
285 #[inline(always)]
286 pub fn down(self) -> &'a mut W {
287 self.variant(AUXCNTEV_A::DOWN)
288 }
289 #[doc = "Counts up on both up-count and down-count events."]
290 #[inline(always)]
291 pub fn both(self) -> &'a mut W {
292 self.variant(AUXCNTEV_A::BOTH)
293 }
294}
295impl R {
296 #[doc = "Bits 0:1 - Mode Select"]
297 #[inline(always)]
298 pub fn mode(&self) -> MODE_R {
299 MODE_R::new((self.bits & 3) as u8)
300 }
301 #[doc = "Bit 2 - Non-Quadrature Mode Counter Direction Control"]
302 #[inline(always)]
303 pub fn cntdir(&self) -> CNTDIR_R {
304 CNTDIR_R::new(((self.bits >> 2) & 1) != 0)
305 }
306 #[doc = "Bit 3 - Edge Select"]
307 #[inline(always)]
308 pub fn edge(&self) -> EDGE_R {
309 EDGE_R::new(((self.bits >> 3) & 1) != 0)
310 }
311 #[doc = "Bit 4 - Enable Digital Pulse Width Filter"]
312 #[inline(always)]
313 pub fn filt(&self) -> FILT_R {
314 FILT_R::new(((self.bits >> 4) & 1) != 0)
315 }
316 #[doc = "Bit 5 - Enable PCNT Clock Domain Reset"]
317 #[inline(always)]
318 pub fn rsten(&self) -> RSTEN_R {
319 RSTEN_R::new(((self.bits >> 5) & 1) != 0)
320 }
321 #[doc = "Bit 8 - Enable Hysteresis"]
322 #[inline(always)]
323 pub fn hyst(&self) -> HYST_R {
324 HYST_R::new(((self.bits >> 8) & 1) != 0)
325 }
326 #[doc = "Bit 9 - Count direction determined by S1"]
327 #[inline(always)]
328 pub fn s1cdir(&self) -> S1CDIR_R {
329 S1CDIR_R::new(((self.bits >> 9) & 1) != 0)
330 }
331 #[doc = "Bits 10:11 - Controls when the counter counts"]
332 #[inline(always)]
333 pub fn cntev(&self) -> CNTEV_R {
334 CNTEV_R::new(((self.bits >> 10) & 3) as u8)
335 }
336 #[doc = "Bits 14:15 - Controls when the auxiliary counter counts"]
337 #[inline(always)]
338 pub fn auxcntev(&self) -> AUXCNTEV_R {
339 AUXCNTEV_R::new(((self.bits >> 14) & 3) as u8)
340 }
341}
342impl W {
343 #[doc = "Bits 0:1 - Mode Select"]
344 #[inline(always)]
345 pub fn mode(&mut self) -> MODE_W {
346 MODE_W::new(self)
347 }
348 #[doc = "Bit 2 - Non-Quadrature Mode Counter Direction Control"]
349 #[inline(always)]
350 pub fn cntdir(&mut self) -> CNTDIR_W {
351 CNTDIR_W::new(self)
352 }
353 #[doc = "Bit 3 - Edge Select"]
354 #[inline(always)]
355 pub fn edge(&mut self) -> EDGE_W {
356 EDGE_W::new(self)
357 }
358 #[doc = "Bit 4 - Enable Digital Pulse Width Filter"]
359 #[inline(always)]
360 pub fn filt(&mut self) -> FILT_W {
361 FILT_W::new(self)
362 }
363 #[doc = "Bit 5 - Enable PCNT Clock Domain Reset"]
364 #[inline(always)]
365 pub fn rsten(&mut self) -> RSTEN_W {
366 RSTEN_W::new(self)
367 }
368 #[doc = "Bit 8 - Enable Hysteresis"]
369 #[inline(always)]
370 pub fn hyst(&mut self) -> HYST_W {
371 HYST_W::new(self)
372 }
373 #[doc = "Bit 9 - Count direction determined by S1"]
374 #[inline(always)]
375 pub fn s1cdir(&mut self) -> S1CDIR_W {
376 S1CDIR_W::new(self)
377 }
378 #[doc = "Bits 10:11 - Controls when the counter counts"]
379 #[inline(always)]
380 pub fn cntev(&mut self) -> CNTEV_W {
381 CNTEV_W::new(self)
382 }
383 #[doc = "Bits 14:15 - Controls when the auxiliary counter counts"]
384 #[inline(always)]
385 pub fn auxcntev(&mut self) -> AUXCNTEV_W {
386 AUXCNTEV_W::new(self)
387 }
388 #[doc = "Writes raw bits to the register."]
389 #[inline(always)]
390 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
391 self.0.bits(bits);
392 self
393 }
394}
395#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
396pub struct CTRL_SPEC;
397impl crate::RegisterSpec for CTRL_SPEC {
398 type Ux = u32;
399}
400#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
401impl crate::Readable for CTRL_SPEC {
402 type Reader = R;
403}
404#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
405impl crate::Writable for CTRL_SPEC {
406 type Writer = W;
407}
408#[doc = "`reset()` method sets CTRL to value 0"]
409impl crate::Resettable for CTRL_SPEC {
410 #[inline(always)]
411 fn reset_value() -> Self::Ux {
412 0
413 }
414}