efm32wg_pac/efm32wg995/timer2/
route.rs

1#[doc = "Register `ROUTE` reader"]
2pub struct R(crate::R<ROUTE_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ROUTE_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ROUTE_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ROUTE_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ROUTE` writer"]
17pub struct W(crate::W<ROUTE_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ROUTE_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ROUTE_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ROUTE_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CC0PEN` reader - CC Channel 0 Pin Enable"]
38pub type CC0PEN_R = crate::BitReader<bool>;
39#[doc = "Field `CC0PEN` writer - CC Channel 0 Pin Enable"]
40pub type CC0PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, O>;
41#[doc = "Field `CC1PEN` reader - CC Channel 1 Pin Enable"]
42pub type CC1PEN_R = crate::BitReader<bool>;
43#[doc = "Field `CC1PEN` writer - CC Channel 1 Pin Enable"]
44pub type CC1PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, O>;
45#[doc = "Field `CC2PEN` reader - CC Channel 2 Pin Enable"]
46pub type CC2PEN_R = crate::BitReader<bool>;
47#[doc = "Field `CC2PEN` writer - CC Channel 2 Pin Enable"]
48pub type CC2PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, O>;
49#[doc = "Field `CDTI0PEN` reader - CC Channel 0 Complementary Dead-Time Insertion Pin Enable"]
50pub type CDTI0PEN_R = crate::BitReader<bool>;
51#[doc = "Field `CDTI0PEN` writer - CC Channel 0 Complementary Dead-Time Insertion Pin Enable"]
52pub type CDTI0PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, O>;
53#[doc = "Field `CDTI1PEN` reader - CC Channel 1 Complementary Dead-Time Insertion Pin Enable"]
54pub type CDTI1PEN_R = crate::BitReader<bool>;
55#[doc = "Field `CDTI1PEN` writer - CC Channel 1 Complementary Dead-Time Insertion Pin Enable"]
56pub type CDTI1PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, O>;
57#[doc = "Field `CDTI2PEN` reader - CC Channel 2 Complementary Dead-Time Insertion Pin Enable"]
58pub type CDTI2PEN_R = crate::BitReader<bool>;
59#[doc = "Field `CDTI2PEN` writer - CC Channel 2 Complementary Dead-Time Insertion Pin Enable"]
60pub type CDTI2PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, O>;
61#[doc = "Field `LOCATION` reader - I/O Location"]
62pub type LOCATION_R = crate::FieldReader<u8, LOCATION_A>;
63#[doc = "I/O Location\n\nValue on reset: 0"]
64#[derive(Clone, Copy, Debug, PartialEq, Eq)]
65#[repr(u8)]
66pub enum LOCATION_A {
67    #[doc = "0: Location 0"]
68    LOC0 = 0,
69    #[doc = "1: Location 1"]
70    LOC1 = 1,
71    #[doc = "2: Location 2"]
72    LOC2 = 2,
73    #[doc = "3: Location 3"]
74    LOC3 = 3,
75    #[doc = "4: Location 4"]
76    LOC4 = 4,
77    #[doc = "5: Location 5"]
78    LOC5 = 5,
79}
80impl From<LOCATION_A> for u8 {
81    #[inline(always)]
82    fn from(variant: LOCATION_A) -> Self {
83        variant as _
84    }
85}
86impl LOCATION_R {
87    #[doc = "Get enumerated values variant"]
88    #[inline(always)]
89    pub fn variant(&self) -> Option<LOCATION_A> {
90        match self.bits {
91            0 => Some(LOCATION_A::LOC0),
92            1 => Some(LOCATION_A::LOC1),
93            2 => Some(LOCATION_A::LOC2),
94            3 => Some(LOCATION_A::LOC3),
95            4 => Some(LOCATION_A::LOC4),
96            5 => Some(LOCATION_A::LOC5),
97            _ => None,
98        }
99    }
100    #[doc = "Checks if the value of the field is `LOC0`"]
101    #[inline(always)]
102    pub fn is_loc0(&self) -> bool {
103        *self == LOCATION_A::LOC0
104    }
105    #[doc = "Checks if the value of the field is `LOC1`"]
106    #[inline(always)]
107    pub fn is_loc1(&self) -> bool {
108        *self == LOCATION_A::LOC1
109    }
110    #[doc = "Checks if the value of the field is `LOC2`"]
111    #[inline(always)]
112    pub fn is_loc2(&self) -> bool {
113        *self == LOCATION_A::LOC2
114    }
115    #[doc = "Checks if the value of the field is `LOC3`"]
116    #[inline(always)]
117    pub fn is_loc3(&self) -> bool {
118        *self == LOCATION_A::LOC3
119    }
120    #[doc = "Checks if the value of the field is `LOC4`"]
121    #[inline(always)]
122    pub fn is_loc4(&self) -> bool {
123        *self == LOCATION_A::LOC4
124    }
125    #[doc = "Checks if the value of the field is `LOC5`"]
126    #[inline(always)]
127    pub fn is_loc5(&self) -> bool {
128        *self == LOCATION_A::LOC5
129    }
130}
131#[doc = "Field `LOCATION` writer - I/O Location"]
132pub type LOCATION_W<'a, const O: u8> =
133    crate::FieldWriter<'a, u32, ROUTE_SPEC, u8, LOCATION_A, 3, O>;
134impl<'a, const O: u8> LOCATION_W<'a, O> {
135    #[doc = "Location 0"]
136    #[inline(always)]
137    pub fn loc0(self) -> &'a mut W {
138        self.variant(LOCATION_A::LOC0)
139    }
140    #[doc = "Location 1"]
141    #[inline(always)]
142    pub fn loc1(self) -> &'a mut W {
143        self.variant(LOCATION_A::LOC1)
144    }
145    #[doc = "Location 2"]
146    #[inline(always)]
147    pub fn loc2(self) -> &'a mut W {
148        self.variant(LOCATION_A::LOC2)
149    }
150    #[doc = "Location 3"]
151    #[inline(always)]
152    pub fn loc3(self) -> &'a mut W {
153        self.variant(LOCATION_A::LOC3)
154    }
155    #[doc = "Location 4"]
156    #[inline(always)]
157    pub fn loc4(self) -> &'a mut W {
158        self.variant(LOCATION_A::LOC4)
159    }
160    #[doc = "Location 5"]
161    #[inline(always)]
162    pub fn loc5(self) -> &'a mut W {
163        self.variant(LOCATION_A::LOC5)
164    }
165}
166impl R {
167    #[doc = "Bit 0 - CC Channel 0 Pin Enable"]
168    #[inline(always)]
169    pub fn cc0pen(&self) -> CC0PEN_R {
170        CC0PEN_R::new((self.bits & 1) != 0)
171    }
172    #[doc = "Bit 1 - CC Channel 1 Pin Enable"]
173    #[inline(always)]
174    pub fn cc1pen(&self) -> CC1PEN_R {
175        CC1PEN_R::new(((self.bits >> 1) & 1) != 0)
176    }
177    #[doc = "Bit 2 - CC Channel 2 Pin Enable"]
178    #[inline(always)]
179    pub fn cc2pen(&self) -> CC2PEN_R {
180        CC2PEN_R::new(((self.bits >> 2) & 1) != 0)
181    }
182    #[doc = "Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable"]
183    #[inline(always)]
184    pub fn cdti0pen(&self) -> CDTI0PEN_R {
185        CDTI0PEN_R::new(((self.bits >> 8) & 1) != 0)
186    }
187    #[doc = "Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable"]
188    #[inline(always)]
189    pub fn cdti1pen(&self) -> CDTI1PEN_R {
190        CDTI1PEN_R::new(((self.bits >> 9) & 1) != 0)
191    }
192    #[doc = "Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable"]
193    #[inline(always)]
194    pub fn cdti2pen(&self) -> CDTI2PEN_R {
195        CDTI2PEN_R::new(((self.bits >> 10) & 1) != 0)
196    }
197    #[doc = "Bits 16:18 - I/O Location"]
198    #[inline(always)]
199    pub fn location(&self) -> LOCATION_R {
200        LOCATION_R::new(((self.bits >> 16) & 7) as u8)
201    }
202}
203impl W {
204    #[doc = "Bit 0 - CC Channel 0 Pin Enable"]
205    #[inline(always)]
206    #[must_use]
207    pub fn cc0pen(&mut self) -> CC0PEN_W<0> {
208        CC0PEN_W::new(self)
209    }
210    #[doc = "Bit 1 - CC Channel 1 Pin Enable"]
211    #[inline(always)]
212    #[must_use]
213    pub fn cc1pen(&mut self) -> CC1PEN_W<1> {
214        CC1PEN_W::new(self)
215    }
216    #[doc = "Bit 2 - CC Channel 2 Pin Enable"]
217    #[inline(always)]
218    #[must_use]
219    pub fn cc2pen(&mut self) -> CC2PEN_W<2> {
220        CC2PEN_W::new(self)
221    }
222    #[doc = "Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable"]
223    #[inline(always)]
224    #[must_use]
225    pub fn cdti0pen(&mut self) -> CDTI0PEN_W<8> {
226        CDTI0PEN_W::new(self)
227    }
228    #[doc = "Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable"]
229    #[inline(always)]
230    #[must_use]
231    pub fn cdti1pen(&mut self) -> CDTI1PEN_W<9> {
232        CDTI1PEN_W::new(self)
233    }
234    #[doc = "Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable"]
235    #[inline(always)]
236    #[must_use]
237    pub fn cdti2pen(&mut self) -> CDTI2PEN_W<10> {
238        CDTI2PEN_W::new(self)
239    }
240    #[doc = "Bits 16:18 - I/O Location"]
241    #[inline(always)]
242    #[must_use]
243    pub fn location(&mut self) -> LOCATION_W<16> {
244        LOCATION_W::new(self)
245    }
246    #[doc = "Writes raw bits to the register."]
247    #[inline(always)]
248    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
249        self.0.bits(bits);
250        self
251    }
252}
253#[doc = "I/O Routing Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [route](index.html) module"]
254pub struct ROUTE_SPEC;
255impl crate::RegisterSpec for ROUTE_SPEC {
256    type Ux = u32;
257}
258#[doc = "`read()` method returns [route::R](R) reader structure"]
259impl crate::Readable for ROUTE_SPEC {
260    type Reader = R;
261}
262#[doc = "`write(|w| ..)` method takes [route::W](W) writer structure"]
263impl crate::Writable for ROUTE_SPEC {
264    type Writer = W;
265    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
266    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
267}
268#[doc = "`reset()` method sets ROUTE to value 0"]
269impl crate::Resettable for ROUTE_SPEC {
270    const RESET_VALUE: Self::Ux = 0;
271}
efm32wg_pac/efm32wg995/timer2/route.rs

efm32wg_pac/efm32wg995/timer2/
route.rs
