efm32tg842_pac/prs/
ch4_ctrl.rs

1#[doc = "Register `CH4_CTRL` reader"]
2pub struct R(crate::R<CH4_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH4_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH4_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH4_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH4_CTRL` writer"]
17pub struct W(crate::W<CH4_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH4_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH4_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH4_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH4_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Voltage Comparator"]
48    VCMP = 1,
49    #[doc = "2: Analog Comparator 0"]
50    ACMP0 = 2,
51    #[doc = "3: Analog Comparator 1"]
52    ACMP1 = 3,
53    #[doc = "6: Digital to Analog Converter 0"]
54    DAC0 = 6,
55    #[doc = "8: Analog to Digital Converter 0"]
56    ADC0 = 8,
57    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
58    USART0 = 16,
59    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
60    USART1 = 17,
61    #[doc = "28: Timer 0"]
62    TIMER0 = 28,
63    #[doc = "29: Timer 1"]
64    TIMER1 = 29,
65    #[doc = "40: Real-Time Counter"]
66    RTC = 40,
67    #[doc = "48: General purpose Input/Output"]
68    GPIOL = 48,
69    #[doc = "49: General purpose Input/Output"]
70    GPIOH = 49,
71    #[doc = "52: Low Energy Timer 0"]
72    LETIMER0 = 52,
73    #[doc = "57: Low Energy Sensor Interface"]
74    LESENSEL = 57,
75    #[doc = "58: Low Energy Sensor Interface"]
76    LESENSEH = 58,
77    #[doc = "59: Low Energy Sensor Interface"]
78    LESENSED = 59,
79}
80impl From<SOURCESEL_A> for u8 {
81    #[inline(always)]
82    fn from(variant: SOURCESEL_A) -> Self {
83        variant as _
84    }
85}
86#[doc = "Field `SOURCESEL` reader - Source Select"]
87pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
88impl SOURCESEL_R {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub fn variant(&self) -> Option<SOURCESEL_A> {
92        match self.bits {
93            0 => Some(SOURCESEL_A::NONE),
94            1 => Some(SOURCESEL_A::VCMP),
95            2 => Some(SOURCESEL_A::ACMP0),
96            3 => Some(SOURCESEL_A::ACMP1),
97            6 => Some(SOURCESEL_A::DAC0),
98            8 => Some(SOURCESEL_A::ADC0),
99            16 => Some(SOURCESEL_A::USART0),
100            17 => Some(SOURCESEL_A::USART1),
101            28 => Some(SOURCESEL_A::TIMER0),
102            29 => Some(SOURCESEL_A::TIMER1),
103            40 => Some(SOURCESEL_A::RTC),
104            48 => Some(SOURCESEL_A::GPIOL),
105            49 => Some(SOURCESEL_A::GPIOH),
106            52 => Some(SOURCESEL_A::LETIMER0),
107            57 => Some(SOURCESEL_A::LESENSEL),
108            58 => Some(SOURCESEL_A::LESENSEH),
109            59 => Some(SOURCESEL_A::LESENSED),
110            _ => None,
111        }
112    }
113    #[doc = "Checks if the value of the field is `NONE`"]
114    #[inline(always)]
115    pub fn is_none(&self) -> bool {
116        *self == SOURCESEL_A::NONE
117    }
118    #[doc = "Checks if the value of the field is `VCMP`"]
119    #[inline(always)]
120    pub fn is_vcmp(&self) -> bool {
121        *self == SOURCESEL_A::VCMP
122    }
123    #[doc = "Checks if the value of the field is `ACMP0`"]
124    #[inline(always)]
125    pub fn is_acmp0(&self) -> bool {
126        *self == SOURCESEL_A::ACMP0
127    }
128    #[doc = "Checks if the value of the field is `ACMP1`"]
129    #[inline(always)]
130    pub fn is_acmp1(&self) -> bool {
131        *self == SOURCESEL_A::ACMP1
132    }
133    #[doc = "Checks if the value of the field is `DAC0`"]
134    #[inline(always)]
135    pub fn is_dac0(&self) -> bool {
136        *self == SOURCESEL_A::DAC0
137    }
138    #[doc = "Checks if the value of the field is `ADC0`"]
139    #[inline(always)]
140    pub fn is_adc0(&self) -> bool {
141        *self == SOURCESEL_A::ADC0
142    }
143    #[doc = "Checks if the value of the field is `USART0`"]
144    #[inline(always)]
145    pub fn is_usart0(&self) -> bool {
146        *self == SOURCESEL_A::USART0
147    }
148    #[doc = "Checks if the value of the field is `USART1`"]
149    #[inline(always)]
150    pub fn is_usart1(&self) -> bool {
151        *self == SOURCESEL_A::USART1
152    }
153    #[doc = "Checks if the value of the field is `TIMER0`"]
154    #[inline(always)]
155    pub fn is_timer0(&self) -> bool {
156        *self == SOURCESEL_A::TIMER0
157    }
158    #[doc = "Checks if the value of the field is `TIMER1`"]
159    #[inline(always)]
160    pub fn is_timer1(&self) -> bool {
161        *self == SOURCESEL_A::TIMER1
162    }
163    #[doc = "Checks if the value of the field is `RTC`"]
164    #[inline(always)]
165    pub fn is_rtc(&self) -> bool {
166        *self == SOURCESEL_A::RTC
167    }
168    #[doc = "Checks if the value of the field is `GPIOL`"]
169    #[inline(always)]
170    pub fn is_gpiol(&self) -> bool {
171        *self == SOURCESEL_A::GPIOL
172    }
173    #[doc = "Checks if the value of the field is `GPIOH`"]
174    #[inline(always)]
175    pub fn is_gpioh(&self) -> bool {
176        *self == SOURCESEL_A::GPIOH
177    }
178    #[doc = "Checks if the value of the field is `LETIMER0`"]
179    #[inline(always)]
180    pub fn is_letimer0(&self) -> bool {
181        *self == SOURCESEL_A::LETIMER0
182    }
183    #[doc = "Checks if the value of the field is `LESENSEL`"]
184    #[inline(always)]
185    pub fn is_lesensel(&self) -> bool {
186        *self == SOURCESEL_A::LESENSEL
187    }
188    #[doc = "Checks if the value of the field is `LESENSEH`"]
189    #[inline(always)]
190    pub fn is_lesenseh(&self) -> bool {
191        *self == SOURCESEL_A::LESENSEH
192    }
193    #[doc = "Checks if the value of the field is `LESENSED`"]
194    #[inline(always)]
195    pub fn is_lesensed(&self) -> bool {
196        *self == SOURCESEL_A::LESENSED
197    }
198}
199#[doc = "Field `SOURCESEL` writer - Source Select"]
200pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH4_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
201impl<'a> SOURCESEL_W<'a> {
202    #[doc = "No source selected"]
203    #[inline(always)]
204    pub fn none(self) -> &'a mut W {
205        self.variant(SOURCESEL_A::NONE)
206    }
207    #[doc = "Voltage Comparator"]
208    #[inline(always)]
209    pub fn vcmp(self) -> &'a mut W {
210        self.variant(SOURCESEL_A::VCMP)
211    }
212    #[doc = "Analog Comparator 0"]
213    #[inline(always)]
214    pub fn acmp0(self) -> &'a mut W {
215        self.variant(SOURCESEL_A::ACMP0)
216    }
217    #[doc = "Analog Comparator 1"]
218    #[inline(always)]
219    pub fn acmp1(self) -> &'a mut W {
220        self.variant(SOURCESEL_A::ACMP1)
221    }
222    #[doc = "Digital to Analog Converter 0"]
223    #[inline(always)]
224    pub fn dac0(self) -> &'a mut W {
225        self.variant(SOURCESEL_A::DAC0)
226    }
227    #[doc = "Analog to Digital Converter 0"]
228    #[inline(always)]
229    pub fn adc0(self) -> &'a mut W {
230        self.variant(SOURCESEL_A::ADC0)
231    }
232    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
233    #[inline(always)]
234    pub fn usart0(self) -> &'a mut W {
235        self.variant(SOURCESEL_A::USART0)
236    }
237    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
238    #[inline(always)]
239    pub fn usart1(self) -> &'a mut W {
240        self.variant(SOURCESEL_A::USART1)
241    }
242    #[doc = "Timer 0"]
243    #[inline(always)]
244    pub fn timer0(self) -> &'a mut W {
245        self.variant(SOURCESEL_A::TIMER0)
246    }
247    #[doc = "Timer 1"]
248    #[inline(always)]
249    pub fn timer1(self) -> &'a mut W {
250        self.variant(SOURCESEL_A::TIMER1)
251    }
252    #[doc = "Real-Time Counter"]
253    #[inline(always)]
254    pub fn rtc(self) -> &'a mut W {
255        self.variant(SOURCESEL_A::RTC)
256    }
257    #[doc = "General purpose Input/Output"]
258    #[inline(always)]
259    pub fn gpiol(self) -> &'a mut W {
260        self.variant(SOURCESEL_A::GPIOL)
261    }
262    #[doc = "General purpose Input/Output"]
263    #[inline(always)]
264    pub fn gpioh(self) -> &'a mut W {
265        self.variant(SOURCESEL_A::GPIOH)
266    }
267    #[doc = "Low Energy Timer 0"]
268    #[inline(always)]
269    pub fn letimer0(self) -> &'a mut W {
270        self.variant(SOURCESEL_A::LETIMER0)
271    }
272    #[doc = "Low Energy Sensor Interface"]
273    #[inline(always)]
274    pub fn lesensel(self) -> &'a mut W {
275        self.variant(SOURCESEL_A::LESENSEL)
276    }
277    #[doc = "Low Energy Sensor Interface"]
278    #[inline(always)]
279    pub fn lesenseh(self) -> &'a mut W {
280        self.variant(SOURCESEL_A::LESENSEH)
281    }
282    #[doc = "Low Energy Sensor Interface"]
283    #[inline(always)]
284    pub fn lesensed(self) -> &'a mut W {
285        self.variant(SOURCESEL_A::LESENSED)
286    }
287}
288#[doc = "Edge Detect Select\n\nValue on reset: 0"]
289#[derive(Clone, Copy, Debug, PartialEq)]
290#[repr(u8)]
291pub enum EDSEL_A {
292    #[doc = "0: Signal is left as it is"]
293    OFF = 0,
294    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
295    POSEDGE = 1,
296    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
297    NEGEDGE = 2,
298    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
299    BOTHEDGES = 3,
300}
301impl From<EDSEL_A> for u8 {
302    #[inline(always)]
303    fn from(variant: EDSEL_A) -> Self {
304        variant as _
305    }
306}
307#[doc = "Field `EDSEL` reader - Edge Detect Select"]
308pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
309impl EDSEL_R {
310    #[doc = "Get enumerated values variant"]
311    #[inline(always)]
312    pub fn variant(&self) -> EDSEL_A {
313        match self.bits {
314            0 => EDSEL_A::OFF,
315            1 => EDSEL_A::POSEDGE,
316            2 => EDSEL_A::NEGEDGE,
317            3 => EDSEL_A::BOTHEDGES,
318            _ => unreachable!(),
319        }
320    }
321    #[doc = "Checks if the value of the field is `OFF`"]
322    #[inline(always)]
323    pub fn is_off(&self) -> bool {
324        *self == EDSEL_A::OFF
325    }
326    #[doc = "Checks if the value of the field is `POSEDGE`"]
327    #[inline(always)]
328    pub fn is_posedge(&self) -> bool {
329        *self == EDSEL_A::POSEDGE
330    }
331    #[doc = "Checks if the value of the field is `NEGEDGE`"]
332    #[inline(always)]
333    pub fn is_negedge(&self) -> bool {
334        *self == EDSEL_A::NEGEDGE
335    }
336    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
337    #[inline(always)]
338    pub fn is_bothedges(&self) -> bool {
339        *self == EDSEL_A::BOTHEDGES
340    }
341}
342#[doc = "Field `EDSEL` writer - Edge Detect Select"]
343pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH4_CTRL_SPEC, u8, EDSEL_A, 2, 24>;
344impl<'a> EDSEL_W<'a> {
345    #[doc = "Signal is left as it is"]
346    #[inline(always)]
347    pub fn off(self) -> &'a mut W {
348        self.variant(EDSEL_A::OFF)
349    }
350    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
351    #[inline(always)]
352    pub fn posedge(self) -> &'a mut W {
353        self.variant(EDSEL_A::POSEDGE)
354    }
355    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
356    #[inline(always)]
357    pub fn negedge(self) -> &'a mut W {
358        self.variant(EDSEL_A::NEGEDGE)
359    }
360    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
361    #[inline(always)]
362    pub fn bothedges(self) -> &'a mut W {
363        self.variant(EDSEL_A::BOTHEDGES)
364    }
365}
366#[doc = "Field `ASYNC` reader - Asynchronous reflex"]
367pub type ASYNC_R = crate::BitReader<bool>;
368#[doc = "Field `ASYNC` writer - Asynchronous reflex"]
369pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH4_CTRL_SPEC, bool, 28>;
370impl R {
371    #[doc = "Bits 0:2 - Signal Select"]
372    #[inline(always)]
373    pub fn sigsel(&self) -> SIGSEL_R {
374        SIGSEL_R::new((self.bits & 7) as u8)
375    }
376    #[doc = "Bits 16:21 - Source Select"]
377    #[inline(always)]
378    pub fn sourcesel(&self) -> SOURCESEL_R {
379        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
380    }
381    #[doc = "Bits 24:25 - Edge Detect Select"]
382    #[inline(always)]
383    pub fn edsel(&self) -> EDSEL_R {
384        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
385    }
386    #[doc = "Bit 28 - Asynchronous reflex"]
387    #[inline(always)]
388    pub fn async_(&self) -> ASYNC_R {
389        ASYNC_R::new(((self.bits >> 28) & 1) != 0)
390    }
391}
392impl W {
393    #[doc = "Bits 0:2 - Signal Select"]
394    #[inline(always)]
395    pub fn sigsel(&mut self) -> SIGSEL_W {
396        SIGSEL_W::new(self)
397    }
398    #[doc = "Bits 16:21 - Source Select"]
399    #[inline(always)]
400    pub fn sourcesel(&mut self) -> SOURCESEL_W {
401        SOURCESEL_W::new(self)
402    }
403    #[doc = "Bits 24:25 - Edge Detect Select"]
404    #[inline(always)]
405    pub fn edsel(&mut self) -> EDSEL_W {
406        EDSEL_W::new(self)
407    }
408    #[doc = "Bit 28 - Asynchronous reflex"]
409    #[inline(always)]
410    pub fn async_(&mut self) -> ASYNC_W {
411        ASYNC_W::new(self)
412    }
413    #[doc = "Writes raw bits to the register."]
414    #[inline(always)]
415    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
416        self.0.bits(bits);
417        self
418    }
419}
420#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch4_ctrl](index.html) module"]
421pub struct CH4_CTRL_SPEC;
422impl crate::RegisterSpec for CH4_CTRL_SPEC {
423    type Ux = u32;
424}
425#[doc = "`read()` method returns [ch4_ctrl::R](R) reader structure"]
426impl crate::Readable for CH4_CTRL_SPEC {
427    type Reader = R;
428}
429#[doc = "`write(|w| ..)` method takes [ch4_ctrl::W](W) writer structure"]
430impl crate::Writable for CH4_CTRL_SPEC {
431    type Writer = W;
432}
433#[doc = "`reset()` method sets CH4_CTRL to value 0"]
434impl crate::Resettable for CH4_CTRL_SPEC {
435    #[inline(always)]
436    fn reset_value() -> Self::Ux {
437        0
438    }
439}
efm32tg842_pac/prs/ch4_ctrl.rs

efm32tg842_pac/prs/
ch4_ctrl.rs
