1#[doc = "Register `PPUPATD0` reader"]
2pub struct R(crate::R<PPUPATD0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<PPUPATD0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<PPUPATD0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<PPUPATD0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `PPUPATD0` writer"]
17pub struct W(crate::W<PPUPATD0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<PPUPATD0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<PPUPATD0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<PPUPATD0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `ACMP0` reader - Analog Comparator 0 access control bit"]
38pub type ACMP0_R = crate::BitReader<bool>;
39#[doc = "Field `ACMP0` writer - Analog Comparator 0 access control bit"]
40pub type ACMP0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 0>;
41#[doc = "Field `ACMP1` reader - Analog Comparator 1 access control bit"]
42pub type ACMP1_R = crate::BitReader<bool>;
43#[doc = "Field `ACMP1` writer - Analog Comparator 1 access control bit"]
44pub type ACMP1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 1>;
45#[doc = "Field `ADC0` reader - Analog to Digital Converter 0 access control bit"]
46pub type ADC0_R = crate::BitReader<bool>;
47#[doc = "Field `ADC0` writer - Analog to Digital Converter 0 access control bit"]
48pub type ADC0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 2>;
49#[doc = "Field `CAN0` reader - CAN 0 access control bit"]
50pub type CAN0_R = crate::BitReader<bool>;
51#[doc = "Field `CAN0` writer - CAN 0 access control bit"]
52pub type CAN0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 3>;
53#[doc = "Field `CMU` reader - Clock Management Unit access control bit"]
54pub type CMU_R = crate::BitReader<bool>;
55#[doc = "Field `CMU` writer - Clock Management Unit access control bit"]
56pub type CMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 4>;
57#[doc = "Field `CRYOTIMER` reader - CRYOTIMER access control bit"]
58pub type CRYOTIMER_R = crate::BitReader<bool>;
59#[doc = "Field `CRYOTIMER` writer - CRYOTIMER access control bit"]
60pub type CRYOTIMER_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 5>;
61#[doc = "Field `CRYPTO0` reader - Advanced Encryption Standard Accelerator access control bit"]
62pub type CRYPTO0_R = crate::BitReader<bool>;
63#[doc = "Field `CRYPTO0` writer - Advanced Encryption Standard Accelerator access control bit"]
64pub type CRYPTO0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 6>;
65#[doc = "Field `CSEN` reader - Capacitive touch sense module access control bit"]
66pub type CSEN_R = crate::BitReader<bool>;
67#[doc = "Field `CSEN` writer - Capacitive touch sense module access control bit"]
68pub type CSEN_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 7>;
69#[doc = "Field `VDAC0` reader - Digital to Analog Converter 0 access control bit"]
70pub type VDAC0_R = crate::BitReader<bool>;
71#[doc = "Field `VDAC0` writer - Digital to Analog Converter 0 access control bit"]
72pub type VDAC0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 8>;
73#[doc = "Field `PRS` reader - Peripheral Reflex System access control bit"]
74pub type PRS_R = crate::BitReader<bool>;
75#[doc = "Field `PRS` writer - Peripheral Reflex System access control bit"]
76pub type PRS_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 9>;
77#[doc = "Field `EMU` reader - Energy Management Unit access control bit"]
78pub type EMU_R = crate::BitReader<bool>;
79#[doc = "Field `EMU` writer - Energy Management Unit access control bit"]
80pub type EMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 10>;
81#[doc = "Field `GPCRC` reader - General Purpose CRC access control bit"]
82pub type GPCRC_R = crate::BitReader<bool>;
83#[doc = "Field `GPCRC` writer - General Purpose CRC access control bit"]
84pub type GPCRC_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 11>;
85#[doc = "Field `GPIO` reader - General purpose Input/Output access control bit"]
86pub type GPIO_R = crate::BitReader<bool>;
87#[doc = "Field `GPIO` writer - General purpose Input/Output access control bit"]
88pub type GPIO_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 12>;
89#[doc = "Field `I2C0` reader - I2C 0 access control bit"]
90pub type I2C0_R = crate::BitReader<bool>;
91#[doc = "Field `I2C0` writer - I2C 0 access control bit"]
92pub type I2C0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 13>;
93#[doc = "Field `I2C1` reader - I2C 1 access control bit"]
94pub type I2C1_R = crate::BitReader<bool>;
95#[doc = "Field `I2C1` writer - I2C 1 access control bit"]
96pub type I2C1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 14>;
97#[doc = "Field `MSC` reader - Memory System Controller access control bit"]
98pub type MSC_R = crate::BitReader<bool>;
99#[doc = "Field `MSC` writer - Memory System Controller access control bit"]
100pub type MSC_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 15>;
101#[doc = "Field `LCD` reader - Liquid Crystal Display Controller access control bit"]
102pub type LCD_R = crate::BitReader<bool>;
103#[doc = "Field `LCD` writer - Liquid Crystal Display Controller access control bit"]
104pub type LCD_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 16>;
105#[doc = "Field `LDMA` reader - Linked Direct Memory Access Controller access control bit"]
106pub type LDMA_R = crate::BitReader<bool>;
107#[doc = "Field `LDMA` writer - Linked Direct Memory Access Controller access control bit"]
108pub type LDMA_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 17>;
109#[doc = "Field `LESENSE` reader - Low Energy Sensor Interface access control bit"]
110pub type LESENSE_R = crate::BitReader<bool>;
111#[doc = "Field `LESENSE` writer - Low Energy Sensor Interface access control bit"]
112pub type LESENSE_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 18>;
113#[doc = "Field `LETIMER0` reader - Low Energy Timer 0 access control bit"]
114pub type LETIMER0_R = crate::BitReader<bool>;
115#[doc = "Field `LETIMER0` writer - Low Energy Timer 0 access control bit"]
116pub type LETIMER0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 19>;
117#[doc = "Field `LEUART0` reader - Low Energy UART 0 access control bit"]
118pub type LEUART0_R = crate::BitReader<bool>;
119#[doc = "Field `LEUART0` writer - Low Energy UART 0 access control bit"]
120pub type LEUART0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 20>;
121#[doc = "Field `PCNT0` reader - Pulse Counter 0 access control bit"]
122pub type PCNT0_R = crate::BitReader<bool>;
123#[doc = "Field `PCNT0` writer - Pulse Counter 0 access control bit"]
124pub type PCNT0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 21>;
125#[doc = "Field `RMU` reader - Reset Management Unit access control bit"]
126pub type RMU_R = crate::BitReader<bool>;
127#[doc = "Field `RMU` writer - Reset Management Unit access control bit"]
128pub type RMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 22>;
129#[doc = "Field `RTCC` reader - Real-Time Counter and Calendar access control bit"]
130pub type RTCC_R = crate::BitReader<bool>;
131#[doc = "Field `RTCC` writer - Real-Time Counter and Calendar access control bit"]
132pub type RTCC_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 23>;
133#[doc = "Field `SMU` reader - Security Management Unit access control bit"]
134pub type SMU_R = crate::BitReader<bool>;
135#[doc = "Field `SMU` writer - Security Management Unit access control bit"]
136pub type SMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 24>;
137#[doc = "Field `TIMER0` reader - Timer 0 access control bit"]
138pub type TIMER0_R = crate::BitReader<bool>;
139#[doc = "Field `TIMER0` writer - Timer 0 access control bit"]
140pub type TIMER0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 25>;
141#[doc = "Field `TIMER1` reader - Timer 1 access control bit"]
142pub type TIMER1_R = crate::BitReader<bool>;
143#[doc = "Field `TIMER1` writer - Timer 1 access control bit"]
144pub type TIMER1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 26>;
145#[doc = "Field `TRNG0` reader - True Random Number Generator 0 access control bit"]
146pub type TRNG0_R = crate::BitReader<bool>;
147#[doc = "Field `TRNG0` writer - True Random Number Generator 0 access control bit"]
148pub type TRNG0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 27>;
149#[doc = "Field `UART0` reader - Universal Asynchronous Receiver/Transmitter 0 access control bit"]
150pub type UART0_R = crate::BitReader<bool>;
151#[doc = "Field `UART0` writer - Universal Asynchronous Receiver/Transmitter 0 access control bit"]
152pub type UART0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 28>;
153#[doc = "Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
154pub type USART0_R = crate::BitReader<bool>;
155#[doc = "Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
156pub type USART0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 29>;
157#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
158pub type USART1_R = crate::BitReader<bool>;
159#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
160pub type USART1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 30>;
161#[doc = "Field `USART2` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
162pub type USART2_R = crate::BitReader<bool>;
163#[doc = "Field `USART2` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
164pub type USART2_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 31>;
165impl R {
166 #[doc = "Bit 0 - Analog Comparator 0 access control bit"]
167 #[inline(always)]
168 pub fn acmp0(&self) -> ACMP0_R {
169 ACMP0_R::new((self.bits & 1) != 0)
170 }
171 #[doc = "Bit 1 - Analog Comparator 1 access control bit"]
172 #[inline(always)]
173 pub fn acmp1(&self) -> ACMP1_R {
174 ACMP1_R::new(((self.bits >> 1) & 1) != 0)
175 }
176 #[doc = "Bit 2 - Analog to Digital Converter 0 access control bit"]
177 #[inline(always)]
178 pub fn adc0(&self) -> ADC0_R {
179 ADC0_R::new(((self.bits >> 2) & 1) != 0)
180 }
181 #[doc = "Bit 3 - CAN 0 access control bit"]
182 #[inline(always)]
183 pub fn can0(&self) -> CAN0_R {
184 CAN0_R::new(((self.bits >> 3) & 1) != 0)
185 }
186 #[doc = "Bit 4 - Clock Management Unit access control bit"]
187 #[inline(always)]
188 pub fn cmu(&self) -> CMU_R {
189 CMU_R::new(((self.bits >> 4) & 1) != 0)
190 }
191 #[doc = "Bit 5 - CRYOTIMER access control bit"]
192 #[inline(always)]
193 pub fn cryotimer(&self) -> CRYOTIMER_R {
194 CRYOTIMER_R::new(((self.bits >> 5) & 1) != 0)
195 }
196 #[doc = "Bit 6 - Advanced Encryption Standard Accelerator access control bit"]
197 #[inline(always)]
198 pub fn crypto0(&self) -> CRYPTO0_R {
199 CRYPTO0_R::new(((self.bits >> 6) & 1) != 0)
200 }
201 #[doc = "Bit 7 - Capacitive touch sense module access control bit"]
202 #[inline(always)]
203 pub fn csen(&self) -> CSEN_R {
204 CSEN_R::new(((self.bits >> 7) & 1) != 0)
205 }
206 #[doc = "Bit 8 - Digital to Analog Converter 0 access control bit"]
207 #[inline(always)]
208 pub fn vdac0(&self) -> VDAC0_R {
209 VDAC0_R::new(((self.bits >> 8) & 1) != 0)
210 }
211 #[doc = "Bit 9 - Peripheral Reflex System access control bit"]
212 #[inline(always)]
213 pub fn prs(&self) -> PRS_R {
214 PRS_R::new(((self.bits >> 9) & 1) != 0)
215 }
216 #[doc = "Bit 10 - Energy Management Unit access control bit"]
217 #[inline(always)]
218 pub fn emu(&self) -> EMU_R {
219 EMU_R::new(((self.bits >> 10) & 1) != 0)
220 }
221 #[doc = "Bit 11 - General Purpose CRC access control bit"]
222 #[inline(always)]
223 pub fn gpcrc(&self) -> GPCRC_R {
224 GPCRC_R::new(((self.bits >> 11) & 1) != 0)
225 }
226 #[doc = "Bit 12 - General purpose Input/Output access control bit"]
227 #[inline(always)]
228 pub fn gpio(&self) -> GPIO_R {
229 GPIO_R::new(((self.bits >> 12) & 1) != 0)
230 }
231 #[doc = "Bit 13 - I2C 0 access control bit"]
232 #[inline(always)]
233 pub fn i2c0(&self) -> I2C0_R {
234 I2C0_R::new(((self.bits >> 13) & 1) != 0)
235 }
236 #[doc = "Bit 14 - I2C 1 access control bit"]
237 #[inline(always)]
238 pub fn i2c1(&self) -> I2C1_R {
239 I2C1_R::new(((self.bits >> 14) & 1) != 0)
240 }
241 #[doc = "Bit 15 - Memory System Controller access control bit"]
242 #[inline(always)]
243 pub fn msc(&self) -> MSC_R {
244 MSC_R::new(((self.bits >> 15) & 1) != 0)
245 }
246 #[doc = "Bit 16 - Liquid Crystal Display Controller access control bit"]
247 #[inline(always)]
248 pub fn lcd(&self) -> LCD_R {
249 LCD_R::new(((self.bits >> 16) & 1) != 0)
250 }
251 #[doc = "Bit 17 - Linked Direct Memory Access Controller access control bit"]
252 #[inline(always)]
253 pub fn ldma(&self) -> LDMA_R {
254 LDMA_R::new(((self.bits >> 17) & 1) != 0)
255 }
256 #[doc = "Bit 18 - Low Energy Sensor Interface access control bit"]
257 #[inline(always)]
258 pub fn lesense(&self) -> LESENSE_R {
259 LESENSE_R::new(((self.bits >> 18) & 1) != 0)
260 }
261 #[doc = "Bit 19 - Low Energy Timer 0 access control bit"]
262 #[inline(always)]
263 pub fn letimer0(&self) -> LETIMER0_R {
264 LETIMER0_R::new(((self.bits >> 19) & 1) != 0)
265 }
266 #[doc = "Bit 20 - Low Energy UART 0 access control bit"]
267 #[inline(always)]
268 pub fn leuart0(&self) -> LEUART0_R {
269 LEUART0_R::new(((self.bits >> 20) & 1) != 0)
270 }
271 #[doc = "Bit 21 - Pulse Counter 0 access control bit"]
272 #[inline(always)]
273 pub fn pcnt0(&self) -> PCNT0_R {
274 PCNT0_R::new(((self.bits >> 21) & 1) != 0)
275 }
276 #[doc = "Bit 22 - Reset Management Unit access control bit"]
277 #[inline(always)]
278 pub fn rmu(&self) -> RMU_R {
279 RMU_R::new(((self.bits >> 22) & 1) != 0)
280 }
281 #[doc = "Bit 23 - Real-Time Counter and Calendar access control bit"]
282 #[inline(always)]
283 pub fn rtcc(&self) -> RTCC_R {
284 RTCC_R::new(((self.bits >> 23) & 1) != 0)
285 }
286 #[doc = "Bit 24 - Security Management Unit access control bit"]
287 #[inline(always)]
288 pub fn smu(&self) -> SMU_R {
289 SMU_R::new(((self.bits >> 24) & 1) != 0)
290 }
291 #[doc = "Bit 25 - Timer 0 access control bit"]
292 #[inline(always)]
293 pub fn timer0(&self) -> TIMER0_R {
294 TIMER0_R::new(((self.bits >> 25) & 1) != 0)
295 }
296 #[doc = "Bit 26 - Timer 1 access control bit"]
297 #[inline(always)]
298 pub fn timer1(&self) -> TIMER1_R {
299 TIMER1_R::new(((self.bits >> 26) & 1) != 0)
300 }
301 #[doc = "Bit 27 - True Random Number Generator 0 access control bit"]
302 #[inline(always)]
303 pub fn trng0(&self) -> TRNG0_R {
304 TRNG0_R::new(((self.bits >> 27) & 1) != 0)
305 }
306 #[doc = "Bit 28 - Universal Asynchronous Receiver/Transmitter 0 access control bit"]
307 #[inline(always)]
308 pub fn uart0(&self) -> UART0_R {
309 UART0_R::new(((self.bits >> 28) & 1) != 0)
310 }
311 #[doc = "Bit 29 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
312 #[inline(always)]
313 pub fn usart0(&self) -> USART0_R {
314 USART0_R::new(((self.bits >> 29) & 1) != 0)
315 }
316 #[doc = "Bit 30 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
317 #[inline(always)]
318 pub fn usart1(&self) -> USART1_R {
319 USART1_R::new(((self.bits >> 30) & 1) != 0)
320 }
321 #[doc = "Bit 31 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
322 #[inline(always)]
323 pub fn usart2(&self) -> USART2_R {
324 USART2_R::new(((self.bits >> 31) & 1) != 0)
325 }
326}
327impl W {
328 #[doc = "Bit 0 - Analog Comparator 0 access control bit"]
329 #[inline(always)]
330 pub fn acmp0(&mut self) -> ACMP0_W {
331 ACMP0_W::new(self)
332 }
333 #[doc = "Bit 1 - Analog Comparator 1 access control bit"]
334 #[inline(always)]
335 pub fn acmp1(&mut self) -> ACMP1_W {
336 ACMP1_W::new(self)
337 }
338 #[doc = "Bit 2 - Analog to Digital Converter 0 access control bit"]
339 #[inline(always)]
340 pub fn adc0(&mut self) -> ADC0_W {
341 ADC0_W::new(self)
342 }
343 #[doc = "Bit 3 - CAN 0 access control bit"]
344 #[inline(always)]
345 pub fn can0(&mut self) -> CAN0_W {
346 CAN0_W::new(self)
347 }
348 #[doc = "Bit 4 - Clock Management Unit access control bit"]
349 #[inline(always)]
350 pub fn cmu(&mut self) -> CMU_W {
351 CMU_W::new(self)
352 }
353 #[doc = "Bit 5 - CRYOTIMER access control bit"]
354 #[inline(always)]
355 pub fn cryotimer(&mut self) -> CRYOTIMER_W {
356 CRYOTIMER_W::new(self)
357 }
358 #[doc = "Bit 6 - Advanced Encryption Standard Accelerator access control bit"]
359 #[inline(always)]
360 pub fn crypto0(&mut self) -> CRYPTO0_W {
361 CRYPTO0_W::new(self)
362 }
363 #[doc = "Bit 7 - Capacitive touch sense module access control bit"]
364 #[inline(always)]
365 pub fn csen(&mut self) -> CSEN_W {
366 CSEN_W::new(self)
367 }
368 #[doc = "Bit 8 - Digital to Analog Converter 0 access control bit"]
369 #[inline(always)]
370 pub fn vdac0(&mut self) -> VDAC0_W {
371 VDAC0_W::new(self)
372 }
373 #[doc = "Bit 9 - Peripheral Reflex System access control bit"]
374 #[inline(always)]
375 pub fn prs(&mut self) -> PRS_W {
376 PRS_W::new(self)
377 }
378 #[doc = "Bit 10 - Energy Management Unit access control bit"]
379 #[inline(always)]
380 pub fn emu(&mut self) -> EMU_W {
381 EMU_W::new(self)
382 }
383 #[doc = "Bit 11 - General Purpose CRC access control bit"]
384 #[inline(always)]
385 pub fn gpcrc(&mut self) -> GPCRC_W {
386 GPCRC_W::new(self)
387 }
388 #[doc = "Bit 12 - General purpose Input/Output access control bit"]
389 #[inline(always)]
390 pub fn gpio(&mut self) -> GPIO_W {
391 GPIO_W::new(self)
392 }
393 #[doc = "Bit 13 - I2C 0 access control bit"]
394 #[inline(always)]
395 pub fn i2c0(&mut self) -> I2C0_W {
396 I2C0_W::new(self)
397 }
398 #[doc = "Bit 14 - I2C 1 access control bit"]
399 #[inline(always)]
400 pub fn i2c1(&mut self) -> I2C1_W {
401 I2C1_W::new(self)
402 }
403 #[doc = "Bit 15 - Memory System Controller access control bit"]
404 #[inline(always)]
405 pub fn msc(&mut self) -> MSC_W {
406 MSC_W::new(self)
407 }
408 #[doc = "Bit 16 - Liquid Crystal Display Controller access control bit"]
409 #[inline(always)]
410 pub fn lcd(&mut self) -> LCD_W {
411 LCD_W::new(self)
412 }
413 #[doc = "Bit 17 - Linked Direct Memory Access Controller access control bit"]
414 #[inline(always)]
415 pub fn ldma(&mut self) -> LDMA_W {
416 LDMA_W::new(self)
417 }
418 #[doc = "Bit 18 - Low Energy Sensor Interface access control bit"]
419 #[inline(always)]
420 pub fn lesense(&mut self) -> LESENSE_W {
421 LESENSE_W::new(self)
422 }
423 #[doc = "Bit 19 - Low Energy Timer 0 access control bit"]
424 #[inline(always)]
425 pub fn letimer0(&mut self) -> LETIMER0_W {
426 LETIMER0_W::new(self)
427 }
428 #[doc = "Bit 20 - Low Energy UART 0 access control bit"]
429 #[inline(always)]
430 pub fn leuart0(&mut self) -> LEUART0_W {
431 LEUART0_W::new(self)
432 }
433 #[doc = "Bit 21 - Pulse Counter 0 access control bit"]
434 #[inline(always)]
435 pub fn pcnt0(&mut self) -> PCNT0_W {
436 PCNT0_W::new(self)
437 }
438 #[doc = "Bit 22 - Reset Management Unit access control bit"]
439 #[inline(always)]
440 pub fn rmu(&mut self) -> RMU_W {
441 RMU_W::new(self)
442 }
443 #[doc = "Bit 23 - Real-Time Counter and Calendar access control bit"]
444 #[inline(always)]
445 pub fn rtcc(&mut self) -> RTCC_W {
446 RTCC_W::new(self)
447 }
448 #[doc = "Bit 24 - Security Management Unit access control bit"]
449 #[inline(always)]
450 pub fn smu(&mut self) -> SMU_W {
451 SMU_W::new(self)
452 }
453 #[doc = "Bit 25 - Timer 0 access control bit"]
454 #[inline(always)]
455 pub fn timer0(&mut self) -> TIMER0_W {
456 TIMER0_W::new(self)
457 }
458 #[doc = "Bit 26 - Timer 1 access control bit"]
459 #[inline(always)]
460 pub fn timer1(&mut self) -> TIMER1_W {
461 TIMER1_W::new(self)
462 }
463 #[doc = "Bit 27 - True Random Number Generator 0 access control bit"]
464 #[inline(always)]
465 pub fn trng0(&mut self) -> TRNG0_W {
466 TRNG0_W::new(self)
467 }
468 #[doc = "Bit 28 - Universal Asynchronous Receiver/Transmitter 0 access control bit"]
469 #[inline(always)]
470 pub fn uart0(&mut self) -> UART0_W {
471 UART0_W::new(self)
472 }
473 #[doc = "Bit 29 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
474 #[inline(always)]
475 pub fn usart0(&mut self) -> USART0_W {
476 USART0_W::new(self)
477 }
478 #[doc = "Bit 30 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
479 #[inline(always)]
480 pub fn usart1(&mut self) -> USART1_W {
481 USART1_W::new(self)
482 }
483 #[doc = "Bit 31 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
484 #[inline(always)]
485 pub fn usart2(&mut self) -> USART2_W {
486 USART2_W::new(self)
487 }
488 #[doc = "Writes raw bits to the register."]
489 #[inline(always)]
490 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
491 self.0.bits(bits);
492 self
493 }
494}
495#[doc = "PPU Privilege Access Type Descriptor 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ppupatd0](index.html) module"]
496pub struct PPUPATD0_SPEC;
497impl crate::RegisterSpec for PPUPATD0_SPEC {
498 type Ux = u32;
499}
500#[doc = "`read()` method returns [ppupatd0::R](R) reader structure"]
501impl crate::Readable for PPUPATD0_SPEC {
502 type Reader = R;
503}
504#[doc = "`write(|w| ..)` method takes [ppupatd0::W](W) writer structure"]
505impl crate::Writable for PPUPATD0_SPEC {
506 type Writer = W;
507}
508#[doc = "`reset()` method sets PPUPATD0 to value 0"]
509impl crate::Resettable for PPUPATD0_SPEC {
510 #[inline(always)]
511 fn reset_value() -> Self::Ux {
512 0
513 }
514}