efm32tg11b540_pac/prs/
ch7_ctrl.rs

1#[doc = "Register `CH7_CTRL` reader"]
2pub struct R(crate::R<CH7_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH7_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH7_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH7_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH7_CTRL` writer"]
17pub struct W(crate::W<CH7_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH7_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH7_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH7_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH7_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Peripheral Reflex System"]
48    PRSL = 1,
49    #[doc = "2: Analog Comparator 0"]
50    ACMP0 = 2,
51    #[doc = "3: Analog Comparator 1"]
52    ACMP1 = 3,
53    #[doc = "4: Analog to Digital Converter 0"]
54    ADC0 = 4,
55    #[doc = "5: Real-Time Counter and Calendar"]
56    RTCC = 5,
57    #[doc = "6: General purpose Input/Output"]
58    GPIOL = 6,
59    #[doc = "7: General purpose Input/Output"]
60    GPIOH = 7,
61    #[doc = "8: Low Energy Timer 0"]
62    LETIMER0 = 8,
63    #[doc = "9: Pulse Counter 0"]
64    PCNT0 = 9,
65    #[doc = "10: CRYOTIMER"]
66    CRYOTIMER = 10,
67    #[doc = "11: Clock Management Unit"]
68    CMU = 11,
69    #[doc = "17: Digital to Analog Converter 0"]
70    VDAC0 = 17,
71    #[doc = "18: Low Energy Sensor Interface"]
72    LESENSEL = 18,
73    #[doc = "19: Low Energy Sensor Interface"]
74    LESENSEH = 19,
75    #[doc = "20: Low Energy Sensor Interface"]
76    LESENSED = 20,
77    #[doc = "21: Low Energy Sensor Interface"]
78    LESENSE = 21,
79    #[doc = "32: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
80    USART0 = 32,
81    #[doc = "33: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
82    USART1 = 33,
83    #[doc = "34: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
84    USART2 = 34,
85    #[doc = "35: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
86    USART3 = 35,
87    #[doc = "36: Universal Asynchronous Receiver/Transmitter 0"]
88    UART0 = 36,
89    #[doc = "37: Timer 0"]
90    TIMER0 = 37,
91    #[doc = "38: Timer 1"]
92    TIMER1 = 38,
93    #[doc = "39: Wide Timer 0"]
94    WTIMER0 = 39,
95    #[doc = "40: Wide Timer 1"]
96    WTIMER1 = 40,
97    #[doc = "41: `101001`"]
98    CM0P = 41,
99}
100impl From<SOURCESEL_A> for u8 {
101    #[inline(always)]
102    fn from(variant: SOURCESEL_A) -> Self {
103        variant as _
104    }
105}
106#[doc = "Field `SOURCESEL` reader - Source Select"]
107pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
108impl SOURCESEL_R {
109    #[doc = "Get enumerated values variant"]
110    #[inline(always)]
111    pub fn variant(&self) -> Option<SOURCESEL_A> {
112        match self.bits {
113            0 => Some(SOURCESEL_A::NONE),
114            1 => Some(SOURCESEL_A::PRSL),
115            2 => Some(SOURCESEL_A::ACMP0),
116            3 => Some(SOURCESEL_A::ACMP1),
117            4 => Some(SOURCESEL_A::ADC0),
118            5 => Some(SOURCESEL_A::RTCC),
119            6 => Some(SOURCESEL_A::GPIOL),
120            7 => Some(SOURCESEL_A::GPIOH),
121            8 => Some(SOURCESEL_A::LETIMER0),
122            9 => Some(SOURCESEL_A::PCNT0),
123            10 => Some(SOURCESEL_A::CRYOTIMER),
124            11 => Some(SOURCESEL_A::CMU),
125            17 => Some(SOURCESEL_A::VDAC0),
126            18 => Some(SOURCESEL_A::LESENSEL),
127            19 => Some(SOURCESEL_A::LESENSEH),
128            20 => Some(SOURCESEL_A::LESENSED),
129            21 => Some(SOURCESEL_A::LESENSE),
130            32 => Some(SOURCESEL_A::USART0),
131            33 => Some(SOURCESEL_A::USART1),
132            34 => Some(SOURCESEL_A::USART2),
133            35 => Some(SOURCESEL_A::USART3),
134            36 => Some(SOURCESEL_A::UART0),
135            37 => Some(SOURCESEL_A::TIMER0),
136            38 => Some(SOURCESEL_A::TIMER1),
137            39 => Some(SOURCESEL_A::WTIMER0),
138            40 => Some(SOURCESEL_A::WTIMER1),
139            41 => Some(SOURCESEL_A::CM0P),
140            _ => None,
141        }
142    }
143    #[doc = "Checks if the value of the field is `NONE`"]
144    #[inline(always)]
145    pub fn is_none(&self) -> bool {
146        *self == SOURCESEL_A::NONE
147    }
148    #[doc = "Checks if the value of the field is `PRSL`"]
149    #[inline(always)]
150    pub fn is_prsl(&self) -> bool {
151        *self == SOURCESEL_A::PRSL
152    }
153    #[doc = "Checks if the value of the field is `ACMP0`"]
154    #[inline(always)]
155    pub fn is_acmp0(&self) -> bool {
156        *self == SOURCESEL_A::ACMP0
157    }
158    #[doc = "Checks if the value of the field is `ACMP1`"]
159    #[inline(always)]
160    pub fn is_acmp1(&self) -> bool {
161        *self == SOURCESEL_A::ACMP1
162    }
163    #[doc = "Checks if the value of the field is `ADC0`"]
164    #[inline(always)]
165    pub fn is_adc0(&self) -> bool {
166        *self == SOURCESEL_A::ADC0
167    }
168    #[doc = "Checks if the value of the field is `RTCC`"]
169    #[inline(always)]
170    pub fn is_rtcc(&self) -> bool {
171        *self == SOURCESEL_A::RTCC
172    }
173    #[doc = "Checks if the value of the field is `GPIOL`"]
174    #[inline(always)]
175    pub fn is_gpiol(&self) -> bool {
176        *self == SOURCESEL_A::GPIOL
177    }
178    #[doc = "Checks if the value of the field is `GPIOH`"]
179    #[inline(always)]
180    pub fn is_gpioh(&self) -> bool {
181        *self == SOURCESEL_A::GPIOH
182    }
183    #[doc = "Checks if the value of the field is `LETIMER0`"]
184    #[inline(always)]
185    pub fn is_letimer0(&self) -> bool {
186        *self == SOURCESEL_A::LETIMER0
187    }
188    #[doc = "Checks if the value of the field is `PCNT0`"]
189    #[inline(always)]
190    pub fn is_pcnt0(&self) -> bool {
191        *self == SOURCESEL_A::PCNT0
192    }
193    #[doc = "Checks if the value of the field is `CRYOTIMER`"]
194    #[inline(always)]
195    pub fn is_cryotimer(&self) -> bool {
196        *self == SOURCESEL_A::CRYOTIMER
197    }
198    #[doc = "Checks if the value of the field is `CMU`"]
199    #[inline(always)]
200    pub fn is_cmu(&self) -> bool {
201        *self == SOURCESEL_A::CMU
202    }
203    #[doc = "Checks if the value of the field is `VDAC0`"]
204    #[inline(always)]
205    pub fn is_vdac0(&self) -> bool {
206        *self == SOURCESEL_A::VDAC0
207    }
208    #[doc = "Checks if the value of the field is `LESENSEL`"]
209    #[inline(always)]
210    pub fn is_lesensel(&self) -> bool {
211        *self == SOURCESEL_A::LESENSEL
212    }
213    #[doc = "Checks if the value of the field is `LESENSEH`"]
214    #[inline(always)]
215    pub fn is_lesenseh(&self) -> bool {
216        *self == SOURCESEL_A::LESENSEH
217    }
218    #[doc = "Checks if the value of the field is `LESENSED`"]
219    #[inline(always)]
220    pub fn is_lesensed(&self) -> bool {
221        *self == SOURCESEL_A::LESENSED
222    }
223    #[doc = "Checks if the value of the field is `LESENSE`"]
224    #[inline(always)]
225    pub fn is_lesense(&self) -> bool {
226        *self == SOURCESEL_A::LESENSE
227    }
228    #[doc = "Checks if the value of the field is `USART0`"]
229    #[inline(always)]
230    pub fn is_usart0(&self) -> bool {
231        *self == SOURCESEL_A::USART0
232    }
233    #[doc = "Checks if the value of the field is `USART1`"]
234    #[inline(always)]
235    pub fn is_usart1(&self) -> bool {
236        *self == SOURCESEL_A::USART1
237    }
238    #[doc = "Checks if the value of the field is `USART2`"]
239    #[inline(always)]
240    pub fn is_usart2(&self) -> bool {
241        *self == SOURCESEL_A::USART2
242    }
243    #[doc = "Checks if the value of the field is `USART3`"]
244    #[inline(always)]
245    pub fn is_usart3(&self) -> bool {
246        *self == SOURCESEL_A::USART3
247    }
248    #[doc = "Checks if the value of the field is `UART0`"]
249    #[inline(always)]
250    pub fn is_uart0(&self) -> bool {
251        *self == SOURCESEL_A::UART0
252    }
253    #[doc = "Checks if the value of the field is `TIMER0`"]
254    #[inline(always)]
255    pub fn is_timer0(&self) -> bool {
256        *self == SOURCESEL_A::TIMER0
257    }
258    #[doc = "Checks if the value of the field is `TIMER1`"]
259    #[inline(always)]
260    pub fn is_timer1(&self) -> bool {
261        *self == SOURCESEL_A::TIMER1
262    }
263    #[doc = "Checks if the value of the field is `WTIMER0`"]
264    #[inline(always)]
265    pub fn is_wtimer0(&self) -> bool {
266        *self == SOURCESEL_A::WTIMER0
267    }
268    #[doc = "Checks if the value of the field is `WTIMER1`"]
269    #[inline(always)]
270    pub fn is_wtimer1(&self) -> bool {
271        *self == SOURCESEL_A::WTIMER1
272    }
273    #[doc = "Checks if the value of the field is `CM0P`"]
274    #[inline(always)]
275    pub fn is_cm0p(&self) -> bool {
276        *self == SOURCESEL_A::CM0P
277    }
278}
279#[doc = "Field `SOURCESEL` writer - Source Select"]
280pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH7_CTRL_SPEC, u8, SOURCESEL_A, 7, 8>;
281impl<'a> SOURCESEL_W<'a> {
282    #[doc = "No source selected"]
283    #[inline(always)]
284    pub fn none(self) -> &'a mut W {
285        self.variant(SOURCESEL_A::NONE)
286    }
287    #[doc = "Peripheral Reflex System"]
288    #[inline(always)]
289    pub fn prsl(self) -> &'a mut W {
290        self.variant(SOURCESEL_A::PRSL)
291    }
292    #[doc = "Analog Comparator 0"]
293    #[inline(always)]
294    pub fn acmp0(self) -> &'a mut W {
295        self.variant(SOURCESEL_A::ACMP0)
296    }
297    #[doc = "Analog Comparator 1"]
298    #[inline(always)]
299    pub fn acmp1(self) -> &'a mut W {
300        self.variant(SOURCESEL_A::ACMP1)
301    }
302    #[doc = "Analog to Digital Converter 0"]
303    #[inline(always)]
304    pub fn adc0(self) -> &'a mut W {
305        self.variant(SOURCESEL_A::ADC0)
306    }
307    #[doc = "Real-Time Counter and Calendar"]
308    #[inline(always)]
309    pub fn rtcc(self) -> &'a mut W {
310        self.variant(SOURCESEL_A::RTCC)
311    }
312    #[doc = "General purpose Input/Output"]
313    #[inline(always)]
314    pub fn gpiol(self) -> &'a mut W {
315        self.variant(SOURCESEL_A::GPIOL)
316    }
317    #[doc = "General purpose Input/Output"]
318    #[inline(always)]
319    pub fn gpioh(self) -> &'a mut W {
320        self.variant(SOURCESEL_A::GPIOH)
321    }
322    #[doc = "Low Energy Timer 0"]
323    #[inline(always)]
324    pub fn letimer0(self) -> &'a mut W {
325        self.variant(SOURCESEL_A::LETIMER0)
326    }
327    #[doc = "Pulse Counter 0"]
328    #[inline(always)]
329    pub fn pcnt0(self) -> &'a mut W {
330        self.variant(SOURCESEL_A::PCNT0)
331    }
332    #[doc = "CRYOTIMER"]
333    #[inline(always)]
334    pub fn cryotimer(self) -> &'a mut W {
335        self.variant(SOURCESEL_A::CRYOTIMER)
336    }
337    #[doc = "Clock Management Unit"]
338    #[inline(always)]
339    pub fn cmu(self) -> &'a mut W {
340        self.variant(SOURCESEL_A::CMU)
341    }
342    #[doc = "Digital to Analog Converter 0"]
343    #[inline(always)]
344    pub fn vdac0(self) -> &'a mut W {
345        self.variant(SOURCESEL_A::VDAC0)
346    }
347    #[doc = "Low Energy Sensor Interface"]
348    #[inline(always)]
349    pub fn lesensel(self) -> &'a mut W {
350        self.variant(SOURCESEL_A::LESENSEL)
351    }
352    #[doc = "Low Energy Sensor Interface"]
353    #[inline(always)]
354    pub fn lesenseh(self) -> &'a mut W {
355        self.variant(SOURCESEL_A::LESENSEH)
356    }
357    #[doc = "Low Energy Sensor Interface"]
358    #[inline(always)]
359    pub fn lesensed(self) -> &'a mut W {
360        self.variant(SOURCESEL_A::LESENSED)
361    }
362    #[doc = "Low Energy Sensor Interface"]
363    #[inline(always)]
364    pub fn lesense(self) -> &'a mut W {
365        self.variant(SOURCESEL_A::LESENSE)
366    }
367    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
368    #[inline(always)]
369    pub fn usart0(self) -> &'a mut W {
370        self.variant(SOURCESEL_A::USART0)
371    }
372    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
373    #[inline(always)]
374    pub fn usart1(self) -> &'a mut W {
375        self.variant(SOURCESEL_A::USART1)
376    }
377    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
378    #[inline(always)]
379    pub fn usart2(self) -> &'a mut W {
380        self.variant(SOURCESEL_A::USART2)
381    }
382    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
383    #[inline(always)]
384    pub fn usart3(self) -> &'a mut W {
385        self.variant(SOURCESEL_A::USART3)
386    }
387    #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
388    #[inline(always)]
389    pub fn uart0(self) -> &'a mut W {
390        self.variant(SOURCESEL_A::UART0)
391    }
392    #[doc = "Timer 0"]
393    #[inline(always)]
394    pub fn timer0(self) -> &'a mut W {
395        self.variant(SOURCESEL_A::TIMER0)
396    }
397    #[doc = "Timer 1"]
398    #[inline(always)]
399    pub fn timer1(self) -> &'a mut W {
400        self.variant(SOURCESEL_A::TIMER1)
401    }
402    #[doc = "Wide Timer 0"]
403    #[inline(always)]
404    pub fn wtimer0(self) -> &'a mut W {
405        self.variant(SOURCESEL_A::WTIMER0)
406    }
407    #[doc = "Wide Timer 1"]
408    #[inline(always)]
409    pub fn wtimer1(self) -> &'a mut W {
410        self.variant(SOURCESEL_A::WTIMER1)
411    }
412    #[doc = "`101001`"]
413    #[inline(always)]
414    pub fn cm0p(self) -> &'a mut W {
415        self.variant(SOURCESEL_A::CM0P)
416    }
417}
418#[doc = "Edge Detect Select\n\nValue on reset: 0"]
419#[derive(Clone, Copy, Debug, PartialEq)]
420#[repr(u8)]
421pub enum EDSEL_A {
422    #[doc = "0: Signal is left as it is"]
423    OFF = 0,
424    #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
425    POSEDGE = 1,
426    #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
427    NEGEDGE = 2,
428    #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
429    BOTHEDGES = 3,
430}
431impl From<EDSEL_A> for u8 {
432    #[inline(always)]
433    fn from(variant: EDSEL_A) -> Self {
434        variant as _
435    }
436}
437#[doc = "Field `EDSEL` reader - Edge Detect Select"]
438pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
439impl EDSEL_R {
440    #[doc = "Get enumerated values variant"]
441    #[inline(always)]
442    pub fn variant(&self) -> EDSEL_A {
443        match self.bits {
444            0 => EDSEL_A::OFF,
445            1 => EDSEL_A::POSEDGE,
446            2 => EDSEL_A::NEGEDGE,
447            3 => EDSEL_A::BOTHEDGES,
448            _ => unreachable!(),
449        }
450    }
451    #[doc = "Checks if the value of the field is `OFF`"]
452    #[inline(always)]
453    pub fn is_off(&self) -> bool {
454        *self == EDSEL_A::OFF
455    }
456    #[doc = "Checks if the value of the field is `POSEDGE`"]
457    #[inline(always)]
458    pub fn is_posedge(&self) -> bool {
459        *self == EDSEL_A::POSEDGE
460    }
461    #[doc = "Checks if the value of the field is `NEGEDGE`"]
462    #[inline(always)]
463    pub fn is_negedge(&self) -> bool {
464        *self == EDSEL_A::NEGEDGE
465    }
466    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
467    #[inline(always)]
468    pub fn is_bothedges(&self) -> bool {
469        *self == EDSEL_A::BOTHEDGES
470    }
471}
472#[doc = "Field `EDSEL` writer - Edge Detect Select"]
473pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH7_CTRL_SPEC, u8, EDSEL_A, 2, 20>;
474impl<'a> EDSEL_W<'a> {
475    #[doc = "Signal is left as it is"]
476    #[inline(always)]
477    pub fn off(self) -> &'a mut W {
478        self.variant(EDSEL_A::OFF)
479    }
480    #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
481    #[inline(always)]
482    pub fn posedge(self) -> &'a mut W {
483        self.variant(EDSEL_A::POSEDGE)
484    }
485    #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
486    #[inline(always)]
487    pub fn negedge(self) -> &'a mut W {
488        self.variant(EDSEL_A::NEGEDGE)
489    }
490    #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
491    #[inline(always)]
492    pub fn bothedges(self) -> &'a mut W {
493        self.variant(EDSEL_A::BOTHEDGES)
494    }
495}
496#[doc = "Field `STRETCH` reader - Stretch Channel Output"]
497pub type STRETCH_R = crate::BitReader<bool>;
498#[doc = "Field `STRETCH` writer - Stretch Channel Output"]
499pub type STRETCH_W<'a> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, 25>;
500#[doc = "Field `INV` reader - Invert Channel"]
501pub type INV_R = crate::BitReader<bool>;
502#[doc = "Field `INV` writer - Invert Channel"]
503pub type INV_W<'a> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, 26>;
504#[doc = "Field `ORPREV` reader - Or Previous"]
505pub type ORPREV_R = crate::BitReader<bool>;
506#[doc = "Field `ORPREV` writer - Or Previous"]
507pub type ORPREV_W<'a> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, 27>;
508#[doc = "Field `ANDNEXT` reader - And Next"]
509pub type ANDNEXT_R = crate::BitReader<bool>;
510#[doc = "Field `ANDNEXT` writer - And Next"]
511pub type ANDNEXT_W<'a> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, 28>;
512#[doc = "Field `ASYNC` reader - Asynchronous Reflex"]
513pub type ASYNC_R = crate::BitReader<bool>;
514#[doc = "Field `ASYNC` writer - Asynchronous Reflex"]
515pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, 30>;
516impl R {
517    #[doc = "Bits 0:2 - Signal Select"]
518    #[inline(always)]
519    pub fn sigsel(&self) -> SIGSEL_R {
520        SIGSEL_R::new((self.bits & 7) as u8)
521    }
522    #[doc = "Bits 8:14 - Source Select"]
523    #[inline(always)]
524    pub fn sourcesel(&self) -> SOURCESEL_R {
525        SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
526    }
527    #[doc = "Bits 20:21 - Edge Detect Select"]
528    #[inline(always)]
529    pub fn edsel(&self) -> EDSEL_R {
530        EDSEL_R::new(((self.bits >> 20) & 3) as u8)
531    }
532    #[doc = "Bit 25 - Stretch Channel Output"]
533    #[inline(always)]
534    pub fn stretch(&self) -> STRETCH_R {
535        STRETCH_R::new(((self.bits >> 25) & 1) != 0)
536    }
537    #[doc = "Bit 26 - Invert Channel"]
538    #[inline(always)]
539    pub fn inv(&self) -> INV_R {
540        INV_R::new(((self.bits >> 26) & 1) != 0)
541    }
542    #[doc = "Bit 27 - Or Previous"]
543    #[inline(always)]
544    pub fn orprev(&self) -> ORPREV_R {
545        ORPREV_R::new(((self.bits >> 27) & 1) != 0)
546    }
547    #[doc = "Bit 28 - And Next"]
548    #[inline(always)]
549    pub fn andnext(&self) -> ANDNEXT_R {
550        ANDNEXT_R::new(((self.bits >> 28) & 1) != 0)
551    }
552    #[doc = "Bit 30 - Asynchronous Reflex"]
553    #[inline(always)]
554    pub fn async_(&self) -> ASYNC_R {
555        ASYNC_R::new(((self.bits >> 30) & 1) != 0)
556    }
557}
558impl W {
559    #[doc = "Bits 0:2 - Signal Select"]
560    #[inline(always)]
561    pub fn sigsel(&mut self) -> SIGSEL_W {
562        SIGSEL_W::new(self)
563    }
564    #[doc = "Bits 8:14 - Source Select"]
565    #[inline(always)]
566    pub fn sourcesel(&mut self) -> SOURCESEL_W {
567        SOURCESEL_W::new(self)
568    }
569    #[doc = "Bits 20:21 - Edge Detect Select"]
570    #[inline(always)]
571    pub fn edsel(&mut self) -> EDSEL_W {
572        EDSEL_W::new(self)
573    }
574    #[doc = "Bit 25 - Stretch Channel Output"]
575    #[inline(always)]
576    pub fn stretch(&mut self) -> STRETCH_W {
577        STRETCH_W::new(self)
578    }
579    #[doc = "Bit 26 - Invert Channel"]
580    #[inline(always)]
581    pub fn inv(&mut self) -> INV_W {
582        INV_W::new(self)
583    }
584    #[doc = "Bit 27 - Or Previous"]
585    #[inline(always)]
586    pub fn orprev(&mut self) -> ORPREV_W {
587        ORPREV_W::new(self)
588    }
589    #[doc = "Bit 28 - And Next"]
590    #[inline(always)]
591    pub fn andnext(&mut self) -> ANDNEXT_W {
592        ANDNEXT_W::new(self)
593    }
594    #[doc = "Bit 30 - Asynchronous Reflex"]
595    #[inline(always)]
596    pub fn async_(&mut self) -> ASYNC_W {
597        ASYNC_W::new(self)
598    }
599    #[doc = "Writes raw bits to the register."]
600    #[inline(always)]
601    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
602        self.0.bits(bits);
603        self
604    }
605}
606#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch7_ctrl](index.html) module"]
607pub struct CH7_CTRL_SPEC;
608impl crate::RegisterSpec for CH7_CTRL_SPEC {
609    type Ux = u32;
610}
611#[doc = "`read()` method returns [ch7_ctrl::R](R) reader structure"]
612impl crate::Readable for CH7_CTRL_SPEC {
613    type Reader = R;
614}
615#[doc = "`write(|w| ..)` method takes [ch7_ctrl::W](W) writer structure"]
616impl crate::Writable for CH7_CTRL_SPEC {
617    type Writer = W;
618}
619#[doc = "`reset()` method sets CH7_CTRL to value 0"]
620impl crate::Resettable for CH7_CTRL_SPEC {
621    #[inline(always)]
622    fn reset_value() -> Self::Ux {
623        0
624    }
625}
efm32tg11b540_pac/prs/ch7_ctrl.rs

efm32tg11b540_pac/prs/
ch7_ctrl.rs
