efm32tg11b540_pac/gpio/
routepen.rs

1#[doc = "Register `ROUTEPEN` reader"]
2pub struct R(crate::R<ROUTEPEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ROUTEPEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ROUTEPEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ROUTEPEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ROUTEPEN` writer"]
17pub struct W(crate::W<ROUTEPEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ROUTEPEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ROUTEPEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ROUTEPEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SWCLKTCKPEN` reader - Serial Wire Clock and JTAG Test Clock Pin Enable"]
38pub type SWCLKTCKPEN_R = crate::BitReader<bool>;
39#[doc = "Field `SWCLKTCKPEN` writer - Serial Wire Clock and JTAG Test Clock Pin Enable"]
40pub type SWCLKTCKPEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 0>;
41#[doc = "Field `SWDIOTMSPEN` reader - Serial Wire Data and JTAG Test Mode Select Pin Enable"]
42pub type SWDIOTMSPEN_R = crate::BitReader<bool>;
43#[doc = "Field `SWDIOTMSPEN` writer - Serial Wire Data and JTAG Test Mode Select Pin Enable"]
44pub type SWDIOTMSPEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 1>;
45#[doc = "Field `TDOPEN` reader - JTAG Test Debug Output Pin Enable"]
46pub type TDOPEN_R = crate::BitReader<bool>;
47#[doc = "Field `TDOPEN` writer - JTAG Test Debug Output Pin Enable"]
48pub type TDOPEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 2>;
49#[doc = "Field `TDIPEN` reader - JTAG Test Debug Input Pin Enable"]
50pub type TDIPEN_R = crate::BitReader<bool>;
51#[doc = "Field `TDIPEN` writer - JTAG Test Debug Input Pin Enable"]
52pub type TDIPEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 3>;
53impl R {
54    #[doc = "Bit 0 - Serial Wire Clock and JTAG Test Clock Pin Enable"]
55    #[inline(always)]
56    pub fn swclktckpen(&self) -> SWCLKTCKPEN_R {
57        SWCLKTCKPEN_R::new((self.bits & 1) != 0)
58    }
59    #[doc = "Bit 1 - Serial Wire Data and JTAG Test Mode Select Pin Enable"]
60    #[inline(always)]
61    pub fn swdiotmspen(&self) -> SWDIOTMSPEN_R {
62        SWDIOTMSPEN_R::new(((self.bits >> 1) & 1) != 0)
63    }
64    #[doc = "Bit 2 - JTAG Test Debug Output Pin Enable"]
65    #[inline(always)]
66    pub fn tdopen(&self) -> TDOPEN_R {
67        TDOPEN_R::new(((self.bits >> 2) & 1) != 0)
68    }
69    #[doc = "Bit 3 - JTAG Test Debug Input Pin Enable"]
70    #[inline(always)]
71    pub fn tdipen(&self) -> TDIPEN_R {
72        TDIPEN_R::new(((self.bits >> 3) & 1) != 0)
73    }
74}
75impl W {
76    #[doc = "Bit 0 - Serial Wire Clock and JTAG Test Clock Pin Enable"]
77    #[inline(always)]
78    pub fn swclktckpen(&mut self) -> SWCLKTCKPEN_W {
79        SWCLKTCKPEN_W::new(self)
80    }
81    #[doc = "Bit 1 - Serial Wire Data and JTAG Test Mode Select Pin Enable"]
82    #[inline(always)]
83    pub fn swdiotmspen(&mut self) -> SWDIOTMSPEN_W {
84        SWDIOTMSPEN_W::new(self)
85    }
86    #[doc = "Bit 2 - JTAG Test Debug Output Pin Enable"]
87    #[inline(always)]
88    pub fn tdopen(&mut self) -> TDOPEN_W {
89        TDOPEN_W::new(self)
90    }
91    #[doc = "Bit 3 - JTAG Test Debug Input Pin Enable"]
92    #[inline(always)]
93    pub fn tdipen(&mut self) -> TDIPEN_W {
94        TDIPEN_W::new(self)
95    }
96    #[doc = "Writes raw bits to the register."]
97    #[inline(always)]
98    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
99        self.0.bits(bits);
100        self
101    }
102}
103#[doc = "I/O Routing Pin Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [routepen](index.html) module"]
104pub struct ROUTEPEN_SPEC;
105impl crate::RegisterSpec for ROUTEPEN_SPEC {
106    type Ux = u32;
107}
108#[doc = "`read()` method returns [routepen::R](R) reader structure"]
109impl crate::Readable for ROUTEPEN_SPEC {
110    type Reader = R;
111}
112#[doc = "`write(|w| ..)` method takes [routepen::W](W) writer structure"]
113impl crate::Writable for ROUTEPEN_SPEC {
114    type Writer = W;
115}
116#[doc = "`reset()` method sets ROUTEPEN to value 0x0f"]
117impl crate::Resettable for ROUTEPEN_SPEC {
118    #[inline(always)]
119    fn reset_value() -> Self::Ux {
120        0x0f
121    }
122}
efm32tg11b540_pac/gpio/routepen.rs

efm32tg11b540_pac/gpio/
routepen.rs
