efm32tg11b540_pac/cmu/
adcctrl.rs

1#[doc = "Register `ADCCTRL` reader"]
2pub struct R(crate::R<ADCCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ADCCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ADCCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ADCCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ADCCTRL` writer"]
17pub struct W(crate::W<ADCCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ADCCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ADCCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ADCCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "ADC0 Clock Prescaler\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum ADC0CLKDIV_A {
41    #[doc = "0: `0`"]
42    NODIVISION = 0,
43}
44impl From<ADC0CLKDIV_A> for u8 {
45    #[inline(always)]
46    fn from(variant: ADC0CLKDIV_A) -> Self {
47        variant as _
48    }
49}
50#[doc = "Field `ADC0CLKDIV` reader - ADC0 Clock Prescaler"]
51pub type ADC0CLKDIV_R = crate::FieldReader<u8, ADC0CLKDIV_A>;
52impl ADC0CLKDIV_R {
53    #[doc = "Get enumerated values variant"]
54    #[inline(always)]
55    pub fn variant(&self) -> Option<ADC0CLKDIV_A> {
56        match self.bits {
57            0 => Some(ADC0CLKDIV_A::NODIVISION),
58            _ => None,
59        }
60    }
61    #[doc = "Checks if the value of the field is `NODIVISION`"]
62    #[inline(always)]
63    pub fn is_nodivision(&self) -> bool {
64        *self == ADC0CLKDIV_A::NODIVISION
65    }
66}
67#[doc = "Field `ADC0CLKDIV` writer - ADC0 Clock Prescaler"]
68pub type ADC0CLKDIV_W<'a> = crate::FieldWriter<'a, u32, ADCCTRL_SPEC, u8, ADC0CLKDIV_A, 2, 0>;
69impl<'a> ADC0CLKDIV_W<'a> {
70    #[doc = "`0`"]
71    #[inline(always)]
72    pub fn nodivision(self) -> &'a mut W {
73        self.variant(ADC0CLKDIV_A::NODIVISION)
74    }
75}
76#[doc = "ADC0 Clock Select\n\nValue on reset: 0"]
77#[derive(Clone, Copy, Debug, PartialEq)]
78#[repr(u8)]
79pub enum ADC0CLKSEL_A {
80    #[doc = "0: ADC0 is not clocked"]
81    DISABLED = 0,
82    #[doc = "1: AUXHFRCO is clocking ADC0"]
83    AUXHFRCO = 1,
84    #[doc = "2: HFXO is clocking ADC0"]
85    HFXO = 2,
86    #[doc = "3: HFSRCCLK is clocking ADC0"]
87    HFSRCCLK = 3,
88}
89impl From<ADC0CLKSEL_A> for u8 {
90    #[inline(always)]
91    fn from(variant: ADC0CLKSEL_A) -> Self {
92        variant as _
93    }
94}
95#[doc = "Field `ADC0CLKSEL` reader - ADC0 Clock Select"]
96pub type ADC0CLKSEL_R = crate::FieldReader<u8, ADC0CLKSEL_A>;
97impl ADC0CLKSEL_R {
98    #[doc = "Get enumerated values variant"]
99    #[inline(always)]
100    pub fn variant(&self) -> ADC0CLKSEL_A {
101        match self.bits {
102            0 => ADC0CLKSEL_A::DISABLED,
103            1 => ADC0CLKSEL_A::AUXHFRCO,
104            2 => ADC0CLKSEL_A::HFXO,
105            3 => ADC0CLKSEL_A::HFSRCCLK,
106            _ => unreachable!(),
107        }
108    }
109    #[doc = "Checks if the value of the field is `DISABLED`"]
110    #[inline(always)]
111    pub fn is_disabled(&self) -> bool {
112        *self == ADC0CLKSEL_A::DISABLED
113    }
114    #[doc = "Checks if the value of the field is `AUXHFRCO`"]
115    #[inline(always)]
116    pub fn is_auxhfrco(&self) -> bool {
117        *self == ADC0CLKSEL_A::AUXHFRCO
118    }
119    #[doc = "Checks if the value of the field is `HFXO`"]
120    #[inline(always)]
121    pub fn is_hfxo(&self) -> bool {
122        *self == ADC0CLKSEL_A::HFXO
123    }
124    #[doc = "Checks if the value of the field is `HFSRCCLK`"]
125    #[inline(always)]
126    pub fn is_hfsrcclk(&self) -> bool {
127        *self == ADC0CLKSEL_A::HFSRCCLK
128    }
129}
130#[doc = "Field `ADC0CLKSEL` writer - ADC0 Clock Select"]
131pub type ADC0CLKSEL_W<'a> = crate::FieldWriterSafe<'a, u32, ADCCTRL_SPEC, u8, ADC0CLKSEL_A, 2, 4>;
132impl<'a> ADC0CLKSEL_W<'a> {
133    #[doc = "ADC0 is not clocked"]
134    #[inline(always)]
135    pub fn disabled(self) -> &'a mut W {
136        self.variant(ADC0CLKSEL_A::DISABLED)
137    }
138    #[doc = "AUXHFRCO is clocking ADC0"]
139    #[inline(always)]
140    pub fn auxhfrco(self) -> &'a mut W {
141        self.variant(ADC0CLKSEL_A::AUXHFRCO)
142    }
143    #[doc = "HFXO is clocking ADC0"]
144    #[inline(always)]
145    pub fn hfxo(self) -> &'a mut W {
146        self.variant(ADC0CLKSEL_A::HFXO)
147    }
148    #[doc = "HFSRCCLK is clocking ADC0"]
149    #[inline(always)]
150    pub fn hfsrcclk(self) -> &'a mut W {
151        self.variant(ADC0CLKSEL_A::HFSRCCLK)
152    }
153}
154#[doc = "Field `ADC0CLKINV` reader - Invert Clock Selected By ADC0CLKSEL"]
155pub type ADC0CLKINV_R = crate::BitReader<bool>;
156#[doc = "Field `ADC0CLKINV` writer - Invert Clock Selected By ADC0CLKSEL"]
157pub type ADC0CLKINV_W<'a> = crate::BitWriter<'a, u32, ADCCTRL_SPEC, bool, 8>;
158impl R {
159    #[doc = "Bits 0:1 - ADC0 Clock Prescaler"]
160    #[inline(always)]
161    pub fn adc0clkdiv(&self) -> ADC0CLKDIV_R {
162        ADC0CLKDIV_R::new((self.bits & 3) as u8)
163    }
164    #[doc = "Bits 4:5 - ADC0 Clock Select"]
165    #[inline(always)]
166    pub fn adc0clksel(&self) -> ADC0CLKSEL_R {
167        ADC0CLKSEL_R::new(((self.bits >> 4) & 3) as u8)
168    }
169    #[doc = "Bit 8 - Invert Clock Selected By ADC0CLKSEL"]
170    #[inline(always)]
171    pub fn adc0clkinv(&self) -> ADC0CLKINV_R {
172        ADC0CLKINV_R::new(((self.bits >> 8) & 1) != 0)
173    }
174}
175impl W {
176    #[doc = "Bits 0:1 - ADC0 Clock Prescaler"]
177    #[inline(always)]
178    pub fn adc0clkdiv(&mut self) -> ADC0CLKDIV_W {
179        ADC0CLKDIV_W::new(self)
180    }
181    #[doc = "Bits 4:5 - ADC0 Clock Select"]
182    #[inline(always)]
183    pub fn adc0clksel(&mut self) -> ADC0CLKSEL_W {
184        ADC0CLKSEL_W::new(self)
185    }
186    #[doc = "Bit 8 - Invert Clock Selected By ADC0CLKSEL"]
187    #[inline(always)]
188    pub fn adc0clkinv(&mut self) -> ADC0CLKINV_W {
189        ADC0CLKINV_W::new(self)
190    }
191    #[doc = "Writes raw bits to the register."]
192    #[inline(always)]
193    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
194        self.0.bits(bits);
195        self
196    }
197}
198#[doc = "ADC Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adcctrl](index.html) module"]
199pub struct ADCCTRL_SPEC;
200impl crate::RegisterSpec for ADCCTRL_SPEC {
201    type Ux = u32;
202}
203#[doc = "`read()` method returns [adcctrl::R](R) reader structure"]
204impl crate::Readable for ADCCTRL_SPEC {
205    type Reader = R;
206}
207#[doc = "`write(|w| ..)` method takes [adcctrl::W](W) writer structure"]
208impl crate::Writable for ADCCTRL_SPEC {
209    type Writer = W;
210}
211#[doc = "`reset()` method sets ADCCTRL to value 0"]
212impl crate::Resettable for ADCCTRL_SPEC {
213    #[inline(always)]
214    fn reset_value() -> Self::Ux {
215        0
216    }
217}
efm32tg11b540_pac/cmu/adcctrl.rs

efm32tg11b540_pac/cmu/
adcctrl.rs
