efm32tg11b540_pac/adc0/
scanctrlx.rs

1#[doc = "Register `SCANCTRLX` reader"]
2pub struct R(crate::R<SCANCTRLX_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SCANCTRLX_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SCANCTRLX_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SCANCTRLX_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SCANCTRLX` writer"]
17pub struct W(crate::W<SCANCTRLX_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SCANCTRLX_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SCANCTRLX_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SCANCTRLX_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Scan Channel Reference Selection\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum VREFSEL_A {
41    #[doc = "0: Internal 0.83V Bandgap reference"]
42    VBGR = 0,
43    #[doc = "1: Scaled AVDD: AVDD*(the VREF attenuation factor)"]
44    VDDXWATT = 1,
45    #[doc = "2: Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenuation factor)"]
46    VREFPWATT = 2,
47    #[doc = "3: Raw single ended external Vref: ADCn_EXTP"]
48    VREFP = 3,
49    #[doc = "5: Scaled differential external Vref from : (ADCn_EXTP-ADCn_EXTN)*(the VREF attenuation factor)"]
50    VREFPNWATT = 5,
51    #[doc = "6: Raw differential external Vref from : (ADCn_EXTP-ADCn_EXTN)"]
52    VREFPN = 6,
53    #[doc = "7: Internal Bandgap reference at low setting 0.78V"]
54    VBGRLOW = 7,
55}
56impl From<VREFSEL_A> for u8 {
57    #[inline(always)]
58    fn from(variant: VREFSEL_A) -> Self {
59        variant as _
60    }
61}
62#[doc = "Field `VREFSEL` reader - Scan Channel Reference Selection"]
63pub type VREFSEL_R = crate::FieldReader<u8, VREFSEL_A>;
64impl VREFSEL_R {
65    #[doc = "Get enumerated values variant"]
66    #[inline(always)]
67    pub fn variant(&self) -> Option<VREFSEL_A> {
68        match self.bits {
69            0 => Some(VREFSEL_A::VBGR),
70            1 => Some(VREFSEL_A::VDDXWATT),
71            2 => Some(VREFSEL_A::VREFPWATT),
72            3 => Some(VREFSEL_A::VREFP),
73            5 => Some(VREFSEL_A::VREFPNWATT),
74            6 => Some(VREFSEL_A::VREFPN),
75            7 => Some(VREFSEL_A::VBGRLOW),
76            _ => None,
77        }
78    }
79    #[doc = "Checks if the value of the field is `VBGR`"]
80    #[inline(always)]
81    pub fn is_vbgr(&self) -> bool {
82        *self == VREFSEL_A::VBGR
83    }
84    #[doc = "Checks if the value of the field is `VDDXWATT`"]
85    #[inline(always)]
86    pub fn is_vddxwatt(&self) -> bool {
87        *self == VREFSEL_A::VDDXWATT
88    }
89    #[doc = "Checks if the value of the field is `VREFPWATT`"]
90    #[inline(always)]
91    pub fn is_vrefpwatt(&self) -> bool {
92        *self == VREFSEL_A::VREFPWATT
93    }
94    #[doc = "Checks if the value of the field is `VREFP`"]
95    #[inline(always)]
96    pub fn is_vrefp(&self) -> bool {
97        *self == VREFSEL_A::VREFP
98    }
99    #[doc = "Checks if the value of the field is `VREFPNWATT`"]
100    #[inline(always)]
101    pub fn is_vrefpnwatt(&self) -> bool {
102        *self == VREFSEL_A::VREFPNWATT
103    }
104    #[doc = "Checks if the value of the field is `VREFPN`"]
105    #[inline(always)]
106    pub fn is_vrefpn(&self) -> bool {
107        *self == VREFSEL_A::VREFPN
108    }
109    #[doc = "Checks if the value of the field is `VBGRLOW`"]
110    #[inline(always)]
111    pub fn is_vbgrlow(&self) -> bool {
112        *self == VREFSEL_A::VBGRLOW
113    }
114}
115#[doc = "Field `VREFSEL` writer - Scan Channel Reference Selection"]
116pub type VREFSEL_W<'a> = crate::FieldWriter<'a, u32, SCANCTRLX_SPEC, u8, VREFSEL_A, 3, 0>;
117impl<'a> VREFSEL_W<'a> {
118    #[doc = "Internal 0.83V Bandgap reference"]
119    #[inline(always)]
120    pub fn vbgr(self) -> &'a mut W {
121        self.variant(VREFSEL_A::VBGR)
122    }
123    #[doc = "Scaled AVDD: AVDD*(the VREF attenuation factor)"]
124    #[inline(always)]
125    pub fn vddxwatt(self) -> &'a mut W {
126        self.variant(VREFSEL_A::VDDXWATT)
127    }
128    #[doc = "Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenuation factor)"]
129    #[inline(always)]
130    pub fn vrefpwatt(self) -> &'a mut W {
131        self.variant(VREFSEL_A::VREFPWATT)
132    }
133    #[doc = "Raw single ended external Vref: ADCn_EXTP"]
134    #[inline(always)]
135    pub fn vrefp(self) -> &'a mut W {
136        self.variant(VREFSEL_A::VREFP)
137    }
138    #[doc = "Scaled differential external Vref from : (ADCn_EXTP-ADCn_EXTN)*(the VREF attenuation factor)"]
139    #[inline(always)]
140    pub fn vrefpnwatt(self) -> &'a mut W {
141        self.variant(VREFSEL_A::VREFPNWATT)
142    }
143    #[doc = "Raw differential external Vref from : (ADCn_EXTP-ADCn_EXTN)"]
144    #[inline(always)]
145    pub fn vrefpn(self) -> &'a mut W {
146        self.variant(VREFSEL_A::VREFPN)
147    }
148    #[doc = "Internal Bandgap reference at low setting 0.78V"]
149    #[inline(always)]
150    pub fn vbgrlow(self) -> &'a mut W {
151        self.variant(VREFSEL_A::VBGRLOW)
152    }
153}
154#[doc = "Field `VREFATTFIX` reader - Enable Fixed Scaling on VREF"]
155pub type VREFATTFIX_R = crate::BitReader<bool>;
156#[doc = "Field `VREFATTFIX` writer - Enable Fixed Scaling on VREF"]
157pub type VREFATTFIX_W<'a> = crate::BitWriter<'a, u32, SCANCTRLX_SPEC, bool, 3>;
158#[doc = "Field `VREFATT` reader - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
159pub type VREFATT_R = crate::FieldReader<u8, u8>;
160#[doc = "Field `VREFATT` writer - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
161pub type VREFATT_W<'a> = crate::FieldWriter<'a, u32, SCANCTRLX_SPEC, u8, u8, 4, 4>;
162#[doc = "Field `VINATT` reader - Code for VIN Attenuation Factor"]
163pub type VINATT_R = crate::FieldReader<u8, u8>;
164#[doc = "Field `VINATT` writer - Code for VIN Attenuation Factor"]
165pub type VINATT_W<'a> = crate::FieldWriter<'a, u32, SCANCTRLX_SPEC, u8, u8, 4, 8>;
166#[doc = "Field `DVL` reader - Scan DV Level Select"]
167pub type DVL_R = crate::FieldReader<u8, u8>;
168#[doc = "Field `DVL` writer - Scan DV Level Select"]
169pub type DVL_W<'a> = crate::FieldWriter<'a, u32, SCANCTRLX_SPEC, u8, u8, 2, 12>;
170#[doc = "Field `FIFOOFACT` reader - Scan FIFO Overflow Action"]
171pub type FIFOOFACT_R = crate::BitReader<bool>;
172#[doc = "Field `FIFOOFACT` writer - Scan FIFO Overflow Action"]
173pub type FIFOOFACT_W<'a> = crate::BitWriter<'a, u32, SCANCTRLX_SPEC, bool, 14>;
174#[doc = "Field `PRSMODE` reader - Scan PRS Trigger Mode"]
175pub type PRSMODE_R = crate::BitReader<bool>;
176#[doc = "Field `PRSMODE` writer - Scan PRS Trigger Mode"]
177pub type PRSMODE_W<'a> = crate::BitWriter<'a, u32, SCANCTRLX_SPEC, bool, 16>;
178#[doc = "Scan Sequence PRS Trigger Select\n\nValue on reset: 0"]
179#[derive(Clone, Copy, Debug, PartialEq)]
180#[repr(u8)]
181pub enum PRSSEL_A {
182    #[doc = "0: PRS ch 0 triggers scan sequence"]
183    PRSCH0 = 0,
184    #[doc = "1: PRS ch 1 triggers scan sequence"]
185    PRSCH1 = 1,
186    #[doc = "2: PRS ch 2 triggers scan sequence"]
187    PRSCH2 = 2,
188    #[doc = "3: PRS ch 3 triggers scan sequence"]
189    PRSCH3 = 3,
190    #[doc = "4: PRS ch 4 triggers scan sequence"]
191    PRSCH4 = 4,
192    #[doc = "5: PRS ch 5 triggers scan sequence"]
193    PRSCH5 = 5,
194    #[doc = "6: PRS ch 6 triggers scan sequence"]
195    PRSCH6 = 6,
196    #[doc = "7: PRS ch 7 triggers scan sequence"]
197    PRSCH7 = 7,
198}
199impl From<PRSSEL_A> for u8 {
200    #[inline(always)]
201    fn from(variant: PRSSEL_A) -> Self {
202        variant as _
203    }
204}
205#[doc = "Field `PRSSEL` reader - Scan Sequence PRS Trigger Select"]
206pub type PRSSEL_R = crate::FieldReader<u8, PRSSEL_A>;
207impl PRSSEL_R {
208    #[doc = "Get enumerated values variant"]
209    #[inline(always)]
210    pub fn variant(&self) -> PRSSEL_A {
211        match self.bits {
212            0 => PRSSEL_A::PRSCH0,
213            1 => PRSSEL_A::PRSCH1,
214            2 => PRSSEL_A::PRSCH2,
215            3 => PRSSEL_A::PRSCH3,
216            4 => PRSSEL_A::PRSCH4,
217            5 => PRSSEL_A::PRSCH5,
218            6 => PRSSEL_A::PRSCH6,
219            7 => PRSSEL_A::PRSCH7,
220            _ => unreachable!(),
221        }
222    }
223    #[doc = "Checks if the value of the field is `PRSCH0`"]
224    #[inline(always)]
225    pub fn is_prsch0(&self) -> bool {
226        *self == PRSSEL_A::PRSCH0
227    }
228    #[doc = "Checks if the value of the field is `PRSCH1`"]
229    #[inline(always)]
230    pub fn is_prsch1(&self) -> bool {
231        *self == PRSSEL_A::PRSCH1
232    }
233    #[doc = "Checks if the value of the field is `PRSCH2`"]
234    #[inline(always)]
235    pub fn is_prsch2(&self) -> bool {
236        *self == PRSSEL_A::PRSCH2
237    }
238    #[doc = "Checks if the value of the field is `PRSCH3`"]
239    #[inline(always)]
240    pub fn is_prsch3(&self) -> bool {
241        *self == PRSSEL_A::PRSCH3
242    }
243    #[doc = "Checks if the value of the field is `PRSCH4`"]
244    #[inline(always)]
245    pub fn is_prsch4(&self) -> bool {
246        *self == PRSSEL_A::PRSCH4
247    }
248    #[doc = "Checks if the value of the field is `PRSCH5`"]
249    #[inline(always)]
250    pub fn is_prsch5(&self) -> bool {
251        *self == PRSSEL_A::PRSCH5
252    }
253    #[doc = "Checks if the value of the field is `PRSCH6`"]
254    #[inline(always)]
255    pub fn is_prsch6(&self) -> bool {
256        *self == PRSSEL_A::PRSCH6
257    }
258    #[doc = "Checks if the value of the field is `PRSCH7`"]
259    #[inline(always)]
260    pub fn is_prsch7(&self) -> bool {
261        *self == PRSSEL_A::PRSCH7
262    }
263}
264#[doc = "Field `PRSSEL` writer - Scan Sequence PRS Trigger Select"]
265pub type PRSSEL_W<'a> = crate::FieldWriterSafe<'a, u32, SCANCTRLX_SPEC, u8, PRSSEL_A, 3, 17>;
266impl<'a> PRSSEL_W<'a> {
267    #[doc = "PRS ch 0 triggers scan sequence"]
268    #[inline(always)]
269    pub fn prsch0(self) -> &'a mut W {
270        self.variant(PRSSEL_A::PRSCH0)
271    }
272    #[doc = "PRS ch 1 triggers scan sequence"]
273    #[inline(always)]
274    pub fn prsch1(self) -> &'a mut W {
275        self.variant(PRSSEL_A::PRSCH1)
276    }
277    #[doc = "PRS ch 2 triggers scan sequence"]
278    #[inline(always)]
279    pub fn prsch2(self) -> &'a mut W {
280        self.variant(PRSSEL_A::PRSCH2)
281    }
282    #[doc = "PRS ch 3 triggers scan sequence"]
283    #[inline(always)]
284    pub fn prsch3(self) -> &'a mut W {
285        self.variant(PRSSEL_A::PRSCH3)
286    }
287    #[doc = "PRS ch 4 triggers scan sequence"]
288    #[inline(always)]
289    pub fn prsch4(self) -> &'a mut W {
290        self.variant(PRSSEL_A::PRSCH4)
291    }
292    #[doc = "PRS ch 5 triggers scan sequence"]
293    #[inline(always)]
294    pub fn prsch5(self) -> &'a mut W {
295        self.variant(PRSSEL_A::PRSCH5)
296    }
297    #[doc = "PRS ch 6 triggers scan sequence"]
298    #[inline(always)]
299    pub fn prsch6(self) -> &'a mut W {
300        self.variant(PRSSEL_A::PRSCH6)
301    }
302    #[doc = "PRS ch 7 triggers scan sequence"]
303    #[inline(always)]
304    pub fn prsch7(self) -> &'a mut W {
305        self.variant(PRSSEL_A::PRSCH7)
306    }
307}
308#[doc = "Field `CONVSTARTDELAY` reader - Delay Next Conversion Start If CONVSTARTDELAYEN is Set"]
309pub type CONVSTARTDELAY_R = crate::FieldReader<u8, u8>;
310#[doc = "Field `CONVSTARTDELAY` writer - Delay Next Conversion Start If CONVSTARTDELAYEN is Set"]
311pub type CONVSTARTDELAY_W<'a> = crate::FieldWriter<'a, u32, SCANCTRLX_SPEC, u8, u8, 5, 22>;
312#[doc = "Field `CONVSTARTDELAYEN` reader - Enable Delaying Next Conversion Start"]
313pub type CONVSTARTDELAYEN_R = crate::BitReader<bool>;
314#[doc = "Field `CONVSTARTDELAYEN` writer - Enable Delaying Next Conversion Start"]
315pub type CONVSTARTDELAYEN_W<'a> = crate::BitWriter<'a, u32, SCANCTRLX_SPEC, bool, 27>;
316#[doc = "REPDELAY Select for SCAN REP Mode\n\nValue on reset: 0"]
317#[derive(Clone, Copy, Debug, PartialEq)]
318#[repr(u8)]
319pub enum REPDELAY_A {
320    #[doc = "0: No delay"]
321    NODELAY = 0,
322    #[doc = "1: 4 conversion clock cycles"]
323    _4CYCLES = 1,
324    #[doc = "2: 8 conversion clock cycles"]
325    _8CYCLES = 2,
326    #[doc = "3: 16 conversion clock cycles"]
327    _16CYCLES = 3,
328    #[doc = "4: 32 conversion clock cycles"]
329    _32CYCLES = 4,
330    #[doc = "5: 64 conversion clock cycles"]
331    _64CYCLES = 5,
332    #[doc = "6: 128 conversion clock cycles"]
333    _128CYCLES = 6,
334    #[doc = "7: 256 conversion clock cycles"]
335    _256CYCLES = 7,
336}
337impl From<REPDELAY_A> for u8 {
338    #[inline(always)]
339    fn from(variant: REPDELAY_A) -> Self {
340        variant as _
341    }
342}
343#[doc = "Field `REPDELAY` reader - REPDELAY Select for SCAN REP Mode"]
344pub type REPDELAY_R = crate::FieldReader<u8, REPDELAY_A>;
345impl REPDELAY_R {
346    #[doc = "Get enumerated values variant"]
347    #[inline(always)]
348    pub fn variant(&self) -> REPDELAY_A {
349        match self.bits {
350            0 => REPDELAY_A::NODELAY,
351            1 => REPDELAY_A::_4CYCLES,
352            2 => REPDELAY_A::_8CYCLES,
353            3 => REPDELAY_A::_16CYCLES,
354            4 => REPDELAY_A::_32CYCLES,
355            5 => REPDELAY_A::_64CYCLES,
356            6 => REPDELAY_A::_128CYCLES,
357            7 => REPDELAY_A::_256CYCLES,
358            _ => unreachable!(),
359        }
360    }
361    #[doc = "Checks if the value of the field is `NODELAY`"]
362    #[inline(always)]
363    pub fn is_nodelay(&self) -> bool {
364        *self == REPDELAY_A::NODELAY
365    }
366    #[doc = "Checks if the value of the field is `_4CYCLES`"]
367    #[inline(always)]
368    pub fn is_4cycles(&self) -> bool {
369        *self == REPDELAY_A::_4CYCLES
370    }
371    #[doc = "Checks if the value of the field is `_8CYCLES`"]
372    #[inline(always)]
373    pub fn is_8cycles(&self) -> bool {
374        *self == REPDELAY_A::_8CYCLES
375    }
376    #[doc = "Checks if the value of the field is `_16CYCLES`"]
377    #[inline(always)]
378    pub fn is_16cycles(&self) -> bool {
379        *self == REPDELAY_A::_16CYCLES
380    }
381    #[doc = "Checks if the value of the field is `_32CYCLES`"]
382    #[inline(always)]
383    pub fn is_32cycles(&self) -> bool {
384        *self == REPDELAY_A::_32CYCLES
385    }
386    #[doc = "Checks if the value of the field is `_64CYCLES`"]
387    #[inline(always)]
388    pub fn is_64cycles(&self) -> bool {
389        *self == REPDELAY_A::_64CYCLES
390    }
391    #[doc = "Checks if the value of the field is `_128CYCLES`"]
392    #[inline(always)]
393    pub fn is_128cycles(&self) -> bool {
394        *self == REPDELAY_A::_128CYCLES
395    }
396    #[doc = "Checks if the value of the field is `_256CYCLES`"]
397    #[inline(always)]
398    pub fn is_256cycles(&self) -> bool {
399        *self == REPDELAY_A::_256CYCLES
400    }
401}
402#[doc = "Field `REPDELAY` writer - REPDELAY Select for SCAN REP Mode"]
403pub type REPDELAY_W<'a> = crate::FieldWriterSafe<'a, u32, SCANCTRLX_SPEC, u8, REPDELAY_A, 3, 29>;
404impl<'a> REPDELAY_W<'a> {
405    #[doc = "No delay"]
406    #[inline(always)]
407    pub fn nodelay(self) -> &'a mut W {
408        self.variant(REPDELAY_A::NODELAY)
409    }
410    #[doc = "4 conversion clock cycles"]
411    #[inline(always)]
412    pub fn _4cycles(self) -> &'a mut W {
413        self.variant(REPDELAY_A::_4CYCLES)
414    }
415    #[doc = "8 conversion clock cycles"]
416    #[inline(always)]
417    pub fn _8cycles(self) -> &'a mut W {
418        self.variant(REPDELAY_A::_8CYCLES)
419    }
420    #[doc = "16 conversion clock cycles"]
421    #[inline(always)]
422    pub fn _16cycles(self) -> &'a mut W {
423        self.variant(REPDELAY_A::_16CYCLES)
424    }
425    #[doc = "32 conversion clock cycles"]
426    #[inline(always)]
427    pub fn _32cycles(self) -> &'a mut W {
428        self.variant(REPDELAY_A::_32CYCLES)
429    }
430    #[doc = "64 conversion clock cycles"]
431    #[inline(always)]
432    pub fn _64cycles(self) -> &'a mut W {
433        self.variant(REPDELAY_A::_64CYCLES)
434    }
435    #[doc = "128 conversion clock cycles"]
436    #[inline(always)]
437    pub fn _128cycles(self) -> &'a mut W {
438        self.variant(REPDELAY_A::_128CYCLES)
439    }
440    #[doc = "256 conversion clock cycles"]
441    #[inline(always)]
442    pub fn _256cycles(self) -> &'a mut W {
443        self.variant(REPDELAY_A::_256CYCLES)
444    }
445}
446impl R {
447    #[doc = "Bits 0:2 - Scan Channel Reference Selection"]
448    #[inline(always)]
449    pub fn vrefsel(&self) -> VREFSEL_R {
450        VREFSEL_R::new((self.bits & 7) as u8)
451    }
452    #[doc = "Bit 3 - Enable Fixed Scaling on VREF"]
453    #[inline(always)]
454    pub fn vrefattfix(&self) -> VREFATTFIX_R {
455        VREFATTFIX_R::new(((self.bits >> 3) & 1) != 0)
456    }
457    #[doc = "Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
458    #[inline(always)]
459    pub fn vrefatt(&self) -> VREFATT_R {
460        VREFATT_R::new(((self.bits >> 4) & 0x0f) as u8)
461    }
462    #[doc = "Bits 8:11 - Code for VIN Attenuation Factor"]
463    #[inline(always)]
464    pub fn vinatt(&self) -> VINATT_R {
465        VINATT_R::new(((self.bits >> 8) & 0x0f) as u8)
466    }
467    #[doc = "Bits 12:13 - Scan DV Level Select"]
468    #[inline(always)]
469    pub fn dvl(&self) -> DVL_R {
470        DVL_R::new(((self.bits >> 12) & 3) as u8)
471    }
472    #[doc = "Bit 14 - Scan FIFO Overflow Action"]
473    #[inline(always)]
474    pub fn fifoofact(&self) -> FIFOOFACT_R {
475        FIFOOFACT_R::new(((self.bits >> 14) & 1) != 0)
476    }
477    #[doc = "Bit 16 - Scan PRS Trigger Mode"]
478    #[inline(always)]
479    pub fn prsmode(&self) -> PRSMODE_R {
480        PRSMODE_R::new(((self.bits >> 16) & 1) != 0)
481    }
482    #[doc = "Bits 17:19 - Scan Sequence PRS Trigger Select"]
483    #[inline(always)]
484    pub fn prssel(&self) -> PRSSEL_R {
485        PRSSEL_R::new(((self.bits >> 17) & 7) as u8)
486    }
487    #[doc = "Bits 22:26 - Delay Next Conversion Start If CONVSTARTDELAYEN is Set"]
488    #[inline(always)]
489    pub fn convstartdelay(&self) -> CONVSTARTDELAY_R {
490        CONVSTARTDELAY_R::new(((self.bits >> 22) & 0x1f) as u8)
491    }
492    #[doc = "Bit 27 - Enable Delaying Next Conversion Start"]
493    #[inline(always)]
494    pub fn convstartdelayen(&self) -> CONVSTARTDELAYEN_R {
495        CONVSTARTDELAYEN_R::new(((self.bits >> 27) & 1) != 0)
496    }
497    #[doc = "Bits 29:31 - REPDELAY Select for SCAN REP Mode"]
498    #[inline(always)]
499    pub fn repdelay(&self) -> REPDELAY_R {
500        REPDELAY_R::new(((self.bits >> 29) & 7) as u8)
501    }
502}
503impl W {
504    #[doc = "Bits 0:2 - Scan Channel Reference Selection"]
505    #[inline(always)]
506    pub fn vrefsel(&mut self) -> VREFSEL_W {
507        VREFSEL_W::new(self)
508    }
509    #[doc = "Bit 3 - Enable Fixed Scaling on VREF"]
510    #[inline(always)]
511    pub fn vrefattfix(&mut self) -> VREFATTFIX_W {
512        VREFATTFIX_W::new(self)
513    }
514    #[doc = "Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
515    #[inline(always)]
516    pub fn vrefatt(&mut self) -> VREFATT_W {
517        VREFATT_W::new(self)
518    }
519    #[doc = "Bits 8:11 - Code for VIN Attenuation Factor"]
520    #[inline(always)]
521    pub fn vinatt(&mut self) -> VINATT_W {
522        VINATT_W::new(self)
523    }
524    #[doc = "Bits 12:13 - Scan DV Level Select"]
525    #[inline(always)]
526    pub fn dvl(&mut self) -> DVL_W {
527        DVL_W::new(self)
528    }
529    #[doc = "Bit 14 - Scan FIFO Overflow Action"]
530    #[inline(always)]
531    pub fn fifoofact(&mut self) -> FIFOOFACT_W {
532        FIFOOFACT_W::new(self)
533    }
534    #[doc = "Bit 16 - Scan PRS Trigger Mode"]
535    #[inline(always)]
536    pub fn prsmode(&mut self) -> PRSMODE_W {
537        PRSMODE_W::new(self)
538    }
539    #[doc = "Bits 17:19 - Scan Sequence PRS Trigger Select"]
540    #[inline(always)]
541    pub fn prssel(&mut self) -> PRSSEL_W {
542        PRSSEL_W::new(self)
543    }
544    #[doc = "Bits 22:26 - Delay Next Conversion Start If CONVSTARTDELAYEN is Set"]
545    #[inline(always)]
546    pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W {
547        CONVSTARTDELAY_W::new(self)
548    }
549    #[doc = "Bit 27 - Enable Delaying Next Conversion Start"]
550    #[inline(always)]
551    pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W {
552        CONVSTARTDELAYEN_W::new(self)
553    }
554    #[doc = "Bits 29:31 - REPDELAY Select for SCAN REP Mode"]
555    #[inline(always)]
556    pub fn repdelay(&mut self) -> REPDELAY_W {
557        REPDELAY_W::new(self)
558    }
559    #[doc = "Writes raw bits to the register."]
560    #[inline(always)]
561    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
562        self.0.bits(bits);
563        self
564    }
565}
566#[doc = "Scan Control Register Continued\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scanctrlx](index.html) module"]
567pub struct SCANCTRLX_SPEC;
568impl crate::RegisterSpec for SCANCTRLX_SPEC {
569    type Ux = u32;
570}
571#[doc = "`read()` method returns [scanctrlx::R](R) reader structure"]
572impl crate::Readable for SCANCTRLX_SPEC {
573    type Reader = R;
574}
575#[doc = "`write(|w| ..)` method takes [scanctrlx::W](W) writer structure"]
576impl crate::Writable for SCANCTRLX_SPEC {
577    type Writer = W;
578}
579#[doc = "`reset()` method sets SCANCTRLX to value 0"]
580impl crate::Resettable for SCANCTRLX_SPEC {
581    #[inline(always)]
582    fn reset_value() -> Self::Ux {
583        0
584    }
585}
efm32tg11b540_pac/adc0/scanctrlx.rs

efm32tg11b540_pac/adc0/
scanctrlx.rs
