efm32tg11b540_pac/cmu/
hfperclken0.rs1#[doc = "Register `HFPERCLKEN0` reader"]
2pub struct R(crate::R<HFPERCLKEN0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<HFPERCLKEN0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<HFPERCLKEN0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<HFPERCLKEN0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `HFPERCLKEN0` writer"]
17pub struct W(crate::W<HFPERCLKEN0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<HFPERCLKEN0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<HFPERCLKEN0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<HFPERCLKEN0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
38pub type USART0_R = crate::BitReader<bool>;
39#[doc = "Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
40pub type USART0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 0>;
41#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
42pub type USART1_R = crate::BitReader<bool>;
43#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
44pub type USART1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 1>;
45#[doc = "Field `USART2` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
46pub type USART2_R = crate::BitReader<bool>;
47#[doc = "Field `USART2` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
48pub type USART2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 2>;
49#[doc = "Field `USART3` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable"]
50pub type USART3_R = crate::BitReader<bool>;
51#[doc = "Field `USART3` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable"]
52pub type USART3_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 3>;
53#[doc = "Field `TIMER0` reader - Timer 0 Clock Enable"]
54pub type TIMER0_R = crate::BitReader<bool>;
55#[doc = "Field `TIMER0` writer - Timer 0 Clock Enable"]
56pub type TIMER0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 4>;
57#[doc = "Field `TIMER1` reader - Timer 1 Clock Enable"]
58pub type TIMER1_R = crate::BitReader<bool>;
59#[doc = "Field `TIMER1` writer - Timer 1 Clock Enable"]
60pub type TIMER1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 5>;
61#[doc = "Field `I2C0` reader - I2C 0 Clock Enable"]
62pub type I2C0_R = crate::BitReader<bool>;
63#[doc = "Field `I2C0` writer - I2C 0 Clock Enable"]
64pub type I2C0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 6>;
65#[doc = "Field `I2C1` reader - I2C 1 Clock Enable"]
66pub type I2C1_R = crate::BitReader<bool>;
67#[doc = "Field `I2C1` writer - I2C 1 Clock Enable"]
68pub type I2C1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 7>;
69#[doc = "Field `ACMP0` reader - Analog Comparator 0 Clock Enable"]
70pub type ACMP0_R = crate::BitReader<bool>;
71#[doc = "Field `ACMP0` writer - Analog Comparator 0 Clock Enable"]
72pub type ACMP0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 8>;
73#[doc = "Field `ACMP1` reader - Analog Comparator 1 Clock Enable"]
74pub type ACMP1_R = crate::BitReader<bool>;
75#[doc = "Field `ACMP1` writer - Analog Comparator 1 Clock Enable"]
76pub type ACMP1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 9>;
77#[doc = "Field `CRYOTIMER` reader - CRYOTIMER Clock Enable"]
78pub type CRYOTIMER_R = crate::BitReader<bool>;
79#[doc = "Field `CRYOTIMER` writer - CRYOTIMER Clock Enable"]
80pub type CRYOTIMER_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 10>;
81#[doc = "Field `ADC0` reader - Analog to Digital Converter 0 Clock Enable"]
82pub type ADC0_R = crate::BitReader<bool>;
83#[doc = "Field `ADC0` writer - Analog to Digital Converter 0 Clock Enable"]
84pub type ADC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 11>;
85#[doc = "Field `TRNG0` reader - True Random Number Generator 0 Clock Enable"]
86pub type TRNG0_R = crate::BitReader<bool>;
87#[doc = "Field `TRNG0` writer - True Random Number Generator 0 Clock Enable"]
88pub type TRNG0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 12>;
89impl R {
90 #[doc = "Bit 0 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
91 #[inline(always)]
92 pub fn usart0(&self) -> USART0_R {
93 USART0_R::new((self.bits & 1) != 0)
94 }
95 #[doc = "Bit 1 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
96 #[inline(always)]
97 pub fn usart1(&self) -> USART1_R {
98 USART1_R::new(((self.bits >> 1) & 1) != 0)
99 }
100 #[doc = "Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
101 #[inline(always)]
102 pub fn usart2(&self) -> USART2_R {
103 USART2_R::new(((self.bits >> 2) & 1) != 0)
104 }
105 #[doc = "Bit 3 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable"]
106 #[inline(always)]
107 pub fn usart3(&self) -> USART3_R {
108 USART3_R::new(((self.bits >> 3) & 1) != 0)
109 }
110 #[doc = "Bit 4 - Timer 0 Clock Enable"]
111 #[inline(always)]
112 pub fn timer0(&self) -> TIMER0_R {
113 TIMER0_R::new(((self.bits >> 4) & 1) != 0)
114 }
115 #[doc = "Bit 5 - Timer 1 Clock Enable"]
116 #[inline(always)]
117 pub fn timer1(&self) -> TIMER1_R {
118 TIMER1_R::new(((self.bits >> 5) & 1) != 0)
119 }
120 #[doc = "Bit 6 - I2C 0 Clock Enable"]
121 #[inline(always)]
122 pub fn i2c0(&self) -> I2C0_R {
123 I2C0_R::new(((self.bits >> 6) & 1) != 0)
124 }
125 #[doc = "Bit 7 - I2C 1 Clock Enable"]
126 #[inline(always)]
127 pub fn i2c1(&self) -> I2C1_R {
128 I2C1_R::new(((self.bits >> 7) & 1) != 0)
129 }
130 #[doc = "Bit 8 - Analog Comparator 0 Clock Enable"]
131 #[inline(always)]
132 pub fn acmp0(&self) -> ACMP0_R {
133 ACMP0_R::new(((self.bits >> 8) & 1) != 0)
134 }
135 #[doc = "Bit 9 - Analog Comparator 1 Clock Enable"]
136 #[inline(always)]
137 pub fn acmp1(&self) -> ACMP1_R {
138 ACMP1_R::new(((self.bits >> 9) & 1) != 0)
139 }
140 #[doc = "Bit 10 - CRYOTIMER Clock Enable"]
141 #[inline(always)]
142 pub fn cryotimer(&self) -> CRYOTIMER_R {
143 CRYOTIMER_R::new(((self.bits >> 10) & 1) != 0)
144 }
145 #[doc = "Bit 11 - Analog to Digital Converter 0 Clock Enable"]
146 #[inline(always)]
147 pub fn adc0(&self) -> ADC0_R {
148 ADC0_R::new(((self.bits >> 11) & 1) != 0)
149 }
150 #[doc = "Bit 12 - True Random Number Generator 0 Clock Enable"]
151 #[inline(always)]
152 pub fn trng0(&self) -> TRNG0_R {
153 TRNG0_R::new(((self.bits >> 12) & 1) != 0)
154 }
155}
156impl W {
157 #[doc = "Bit 0 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
158 #[inline(always)]
159 pub fn usart0(&mut self) -> USART0_W {
160 USART0_W::new(self)
161 }
162 #[doc = "Bit 1 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
163 #[inline(always)]
164 pub fn usart1(&mut self) -> USART1_W {
165 USART1_W::new(self)
166 }
167 #[doc = "Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
168 #[inline(always)]
169 pub fn usart2(&mut self) -> USART2_W {
170 USART2_W::new(self)
171 }
172 #[doc = "Bit 3 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable"]
173 #[inline(always)]
174 pub fn usart3(&mut self) -> USART3_W {
175 USART3_W::new(self)
176 }
177 #[doc = "Bit 4 - Timer 0 Clock Enable"]
178 #[inline(always)]
179 pub fn timer0(&mut self) -> TIMER0_W {
180 TIMER0_W::new(self)
181 }
182 #[doc = "Bit 5 - Timer 1 Clock Enable"]
183 #[inline(always)]
184 pub fn timer1(&mut self) -> TIMER1_W {
185 TIMER1_W::new(self)
186 }
187 #[doc = "Bit 6 - I2C 0 Clock Enable"]
188 #[inline(always)]
189 pub fn i2c0(&mut self) -> I2C0_W {
190 I2C0_W::new(self)
191 }
192 #[doc = "Bit 7 - I2C 1 Clock Enable"]
193 #[inline(always)]
194 pub fn i2c1(&mut self) -> I2C1_W {
195 I2C1_W::new(self)
196 }
197 #[doc = "Bit 8 - Analog Comparator 0 Clock Enable"]
198 #[inline(always)]
199 pub fn acmp0(&mut self) -> ACMP0_W {
200 ACMP0_W::new(self)
201 }
202 #[doc = "Bit 9 - Analog Comparator 1 Clock Enable"]
203 #[inline(always)]
204 pub fn acmp1(&mut self) -> ACMP1_W {
205 ACMP1_W::new(self)
206 }
207 #[doc = "Bit 10 - CRYOTIMER Clock Enable"]
208 #[inline(always)]
209 pub fn cryotimer(&mut self) -> CRYOTIMER_W {
210 CRYOTIMER_W::new(self)
211 }
212 #[doc = "Bit 11 - Analog to Digital Converter 0 Clock Enable"]
213 #[inline(always)]
214 pub fn adc0(&mut self) -> ADC0_W {
215 ADC0_W::new(self)
216 }
217 #[doc = "Bit 12 - True Random Number Generator 0 Clock Enable"]
218 #[inline(always)]
219 pub fn trng0(&mut self) -> TRNG0_W {
220 TRNG0_W::new(self)
221 }
222 #[doc = "Writes raw bits to the register."]
223 #[inline(always)]
224 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
225 self.0.bits(bits);
226 self
227 }
228}
229#[doc = "High Frequency Peripheral Clock Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfperclken0](index.html) module"]
230pub struct HFPERCLKEN0_SPEC;
231impl crate::RegisterSpec for HFPERCLKEN0_SPEC {
232 type Ux = u32;
233}
234#[doc = "`read()` method returns [hfperclken0::R](R) reader structure"]
235impl crate::Readable for HFPERCLKEN0_SPEC {
236 type Reader = R;
237}
238#[doc = "`write(|w| ..)` method takes [hfperclken0::W](W) writer structure"]
239impl crate::Writable for HFPERCLKEN0_SPEC {
240 type Writer = W;
241}
242#[doc = "`reset()` method sets HFPERCLKEN0 to value 0"]
243impl crate::Resettable for HFPERCLKEN0_SPEC {
244 #[inline(always)]
245 fn reset_value() -> Self::Ux {
246 0
247 }
248}