efm32tg11b520_pac/vdac0/
ch1ctrl.rs

1#[doc = "Register `CH1CTRL` reader"]
2pub struct R(crate::R<CH1CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH1CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH1CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH1CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH1CTRL` writer"]
17pub struct W(crate::W<CH1CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH1CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH1CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH1CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CONVMODE` reader - Conversion Mode"]
38pub type CONVMODE_R = crate::BitReader<bool>;
39#[doc = "Field `CONVMODE` writer - Conversion Mode"]
40pub type CONVMODE_W<'a> = crate::BitWriter<'a, u32, CH1CTRL_SPEC, bool, 0>;
41#[doc = "Channel 1 Trigger Mode\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum TRIGMODE_A {
45    #[doc = "0: Channel 1 is triggered by CH1DATA or COMBDATA write"]
46    SW = 0,
47    #[doc = "1: Channel 1 is triggered by PRS input"]
48    PRS = 1,
49    #[doc = "2: Channel 1 is triggered by Refresh timer"]
50    REFRESH = 2,
51    #[doc = "3: Channel 1 is triggered by CH1DATA/COMBDATA write or PRS input"]
52    SWPRS = 3,
53    #[doc = "4: Channel 1 is triggered by CH1DATA/COMBDATA write or Refresh timer"]
54    SWREFRESH = 4,
55    #[doc = "5: Channel 1 is triggered by LESENSE"]
56    LESENSE = 5,
57}
58impl From<TRIGMODE_A> for u8 {
59    #[inline(always)]
60    fn from(variant: TRIGMODE_A) -> Self {
61        variant as _
62    }
63}
64#[doc = "Field `TRIGMODE` reader - Channel 1 Trigger Mode"]
65pub type TRIGMODE_R = crate::FieldReader<u8, TRIGMODE_A>;
66impl TRIGMODE_R {
67    #[doc = "Get enumerated values variant"]
68    #[inline(always)]
69    pub fn variant(&self) -> Option<TRIGMODE_A> {
70        match self.bits {
71            0 => Some(TRIGMODE_A::SW),
72            1 => Some(TRIGMODE_A::PRS),
73            2 => Some(TRIGMODE_A::REFRESH),
74            3 => Some(TRIGMODE_A::SWPRS),
75            4 => Some(TRIGMODE_A::SWREFRESH),
76            5 => Some(TRIGMODE_A::LESENSE),
77            _ => None,
78        }
79    }
80    #[doc = "Checks if the value of the field is `SW`"]
81    #[inline(always)]
82    pub fn is_sw(&self) -> bool {
83        *self == TRIGMODE_A::SW
84    }
85    #[doc = "Checks if the value of the field is `PRS`"]
86    #[inline(always)]
87    pub fn is_prs(&self) -> bool {
88        *self == TRIGMODE_A::PRS
89    }
90    #[doc = "Checks if the value of the field is `REFRESH`"]
91    #[inline(always)]
92    pub fn is_refresh(&self) -> bool {
93        *self == TRIGMODE_A::REFRESH
94    }
95    #[doc = "Checks if the value of the field is `SWPRS`"]
96    #[inline(always)]
97    pub fn is_swprs(&self) -> bool {
98        *self == TRIGMODE_A::SWPRS
99    }
100    #[doc = "Checks if the value of the field is `SWREFRESH`"]
101    #[inline(always)]
102    pub fn is_swrefresh(&self) -> bool {
103        *self == TRIGMODE_A::SWREFRESH
104    }
105    #[doc = "Checks if the value of the field is `LESENSE`"]
106    #[inline(always)]
107    pub fn is_lesense(&self) -> bool {
108        *self == TRIGMODE_A::LESENSE
109    }
110}
111#[doc = "Field `TRIGMODE` writer - Channel 1 Trigger Mode"]
112pub type TRIGMODE_W<'a> = crate::FieldWriter<'a, u32, CH1CTRL_SPEC, u8, TRIGMODE_A, 3, 4>;
113impl<'a> TRIGMODE_W<'a> {
114    #[doc = "Channel 1 is triggered by CH1DATA or COMBDATA write"]
115    #[inline(always)]
116    pub fn sw(self) -> &'a mut W {
117        self.variant(TRIGMODE_A::SW)
118    }
119    #[doc = "Channel 1 is triggered by PRS input"]
120    #[inline(always)]
121    pub fn prs(self) -> &'a mut W {
122        self.variant(TRIGMODE_A::PRS)
123    }
124    #[doc = "Channel 1 is triggered by Refresh timer"]
125    #[inline(always)]
126    pub fn refresh(self) -> &'a mut W {
127        self.variant(TRIGMODE_A::REFRESH)
128    }
129    #[doc = "Channel 1 is triggered by CH1DATA/COMBDATA write or PRS input"]
130    #[inline(always)]
131    pub fn swprs(self) -> &'a mut W {
132        self.variant(TRIGMODE_A::SWPRS)
133    }
134    #[doc = "Channel 1 is triggered by CH1DATA/COMBDATA write or Refresh timer"]
135    #[inline(always)]
136    pub fn swrefresh(self) -> &'a mut W {
137        self.variant(TRIGMODE_A::SWREFRESH)
138    }
139    #[doc = "Channel 1 is triggered by LESENSE"]
140    #[inline(always)]
141    pub fn lesense(self) -> &'a mut W {
142        self.variant(TRIGMODE_A::LESENSE)
143    }
144}
145#[doc = "Field `PRSASYNC` reader - Channel 1 PRS Asynchronous Enable"]
146pub type PRSASYNC_R = crate::BitReader<bool>;
147#[doc = "Field `PRSASYNC` writer - Channel 1 PRS Asynchronous Enable"]
148pub type PRSASYNC_W<'a> = crate::BitWriter<'a, u32, CH1CTRL_SPEC, bool, 8>;
149#[doc = "Channel 1 PRS Trigger Select\n\nValue on reset: 0"]
150#[derive(Clone, Copy, Debug, PartialEq)]
151#[repr(u8)]
152pub enum PRSSEL_A {
153    #[doc = "0: PRS ch 0 triggers a conversion."]
154    PRSCH0 = 0,
155    #[doc = "1: PRS ch 1 triggers a conversion."]
156    PRSCH1 = 1,
157    #[doc = "2: PRS ch 2 triggers a conversion."]
158    PRSCH2 = 2,
159    #[doc = "3: PRS ch 3 triggers a conversion."]
160    PRSCH3 = 3,
161    #[doc = "4: PRS ch 4 triggers a conversion."]
162    PRSCH4 = 4,
163    #[doc = "5: PRS ch 5 triggers a conversion."]
164    PRSCH5 = 5,
165    #[doc = "6: PRS ch 6 triggers a conversion."]
166    PRSCH6 = 6,
167    #[doc = "7: PRS ch 7 triggers a conversion."]
168    PRSCH7 = 7,
169}
170impl From<PRSSEL_A> for u8 {
171    #[inline(always)]
172    fn from(variant: PRSSEL_A) -> Self {
173        variant as _
174    }
175}
176#[doc = "Field `PRSSEL` reader - Channel 1 PRS Trigger Select"]
177pub type PRSSEL_R = crate::FieldReader<u8, PRSSEL_A>;
178impl PRSSEL_R {
179    #[doc = "Get enumerated values variant"]
180    #[inline(always)]
181    pub fn variant(&self) -> PRSSEL_A {
182        match self.bits {
183            0 => PRSSEL_A::PRSCH0,
184            1 => PRSSEL_A::PRSCH1,
185            2 => PRSSEL_A::PRSCH2,
186            3 => PRSSEL_A::PRSCH3,
187            4 => PRSSEL_A::PRSCH4,
188            5 => PRSSEL_A::PRSCH5,
189            6 => PRSSEL_A::PRSCH6,
190            7 => PRSSEL_A::PRSCH7,
191            _ => unreachable!(),
192        }
193    }
194    #[doc = "Checks if the value of the field is `PRSCH0`"]
195    #[inline(always)]
196    pub fn is_prsch0(&self) -> bool {
197        *self == PRSSEL_A::PRSCH0
198    }
199    #[doc = "Checks if the value of the field is `PRSCH1`"]
200    #[inline(always)]
201    pub fn is_prsch1(&self) -> bool {
202        *self == PRSSEL_A::PRSCH1
203    }
204    #[doc = "Checks if the value of the field is `PRSCH2`"]
205    #[inline(always)]
206    pub fn is_prsch2(&self) -> bool {
207        *self == PRSSEL_A::PRSCH2
208    }
209    #[doc = "Checks if the value of the field is `PRSCH3`"]
210    #[inline(always)]
211    pub fn is_prsch3(&self) -> bool {
212        *self == PRSSEL_A::PRSCH3
213    }
214    #[doc = "Checks if the value of the field is `PRSCH4`"]
215    #[inline(always)]
216    pub fn is_prsch4(&self) -> bool {
217        *self == PRSSEL_A::PRSCH4
218    }
219    #[doc = "Checks if the value of the field is `PRSCH5`"]
220    #[inline(always)]
221    pub fn is_prsch5(&self) -> bool {
222        *self == PRSSEL_A::PRSCH5
223    }
224    #[doc = "Checks if the value of the field is `PRSCH6`"]
225    #[inline(always)]
226    pub fn is_prsch6(&self) -> bool {
227        *self == PRSSEL_A::PRSCH6
228    }
229    #[doc = "Checks if the value of the field is `PRSCH7`"]
230    #[inline(always)]
231    pub fn is_prsch7(&self) -> bool {
232        *self == PRSSEL_A::PRSCH7
233    }
234}
235#[doc = "Field `PRSSEL` writer - Channel 1 PRS Trigger Select"]
236pub type PRSSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH1CTRL_SPEC, u8, PRSSEL_A, 3, 12>;
237impl<'a> PRSSEL_W<'a> {
238    #[doc = "PRS ch 0 triggers a conversion."]
239    #[inline(always)]
240    pub fn prsch0(self) -> &'a mut W {
241        self.variant(PRSSEL_A::PRSCH0)
242    }
243    #[doc = "PRS ch 1 triggers a conversion."]
244    #[inline(always)]
245    pub fn prsch1(self) -> &'a mut W {
246        self.variant(PRSSEL_A::PRSCH1)
247    }
248    #[doc = "PRS ch 2 triggers a conversion."]
249    #[inline(always)]
250    pub fn prsch2(self) -> &'a mut W {
251        self.variant(PRSSEL_A::PRSCH2)
252    }
253    #[doc = "PRS ch 3 triggers a conversion."]
254    #[inline(always)]
255    pub fn prsch3(self) -> &'a mut W {
256        self.variant(PRSSEL_A::PRSCH3)
257    }
258    #[doc = "PRS ch 4 triggers a conversion."]
259    #[inline(always)]
260    pub fn prsch4(self) -> &'a mut W {
261        self.variant(PRSSEL_A::PRSCH4)
262    }
263    #[doc = "PRS ch 5 triggers a conversion."]
264    #[inline(always)]
265    pub fn prsch5(self) -> &'a mut W {
266        self.variant(PRSSEL_A::PRSCH5)
267    }
268    #[doc = "PRS ch 6 triggers a conversion."]
269    #[inline(always)]
270    pub fn prsch6(self) -> &'a mut W {
271        self.variant(PRSSEL_A::PRSCH6)
272    }
273    #[doc = "PRS ch 7 triggers a conversion."]
274    #[inline(always)]
275    pub fn prsch7(self) -> &'a mut W {
276        self.variant(PRSSEL_A::PRSCH7)
277    }
278}
279impl R {
280    #[doc = "Bit 0 - Conversion Mode"]
281    #[inline(always)]
282    pub fn convmode(&self) -> CONVMODE_R {
283        CONVMODE_R::new((self.bits & 1) != 0)
284    }
285    #[doc = "Bits 4:6 - Channel 1 Trigger Mode"]
286    #[inline(always)]
287    pub fn trigmode(&self) -> TRIGMODE_R {
288        TRIGMODE_R::new(((self.bits >> 4) & 7) as u8)
289    }
290    #[doc = "Bit 8 - Channel 1 PRS Asynchronous Enable"]
291    #[inline(always)]
292    pub fn prsasync(&self) -> PRSASYNC_R {
293        PRSASYNC_R::new(((self.bits >> 8) & 1) != 0)
294    }
295    #[doc = "Bits 12:14 - Channel 1 PRS Trigger Select"]
296    #[inline(always)]
297    pub fn prssel(&self) -> PRSSEL_R {
298        PRSSEL_R::new(((self.bits >> 12) & 7) as u8)
299    }
300}
301impl W {
302    #[doc = "Bit 0 - Conversion Mode"]
303    #[inline(always)]
304    pub fn convmode(&mut self) -> CONVMODE_W {
305        CONVMODE_W::new(self)
306    }
307    #[doc = "Bits 4:6 - Channel 1 Trigger Mode"]
308    #[inline(always)]
309    pub fn trigmode(&mut self) -> TRIGMODE_W {
310        TRIGMODE_W::new(self)
311    }
312    #[doc = "Bit 8 - Channel 1 PRS Asynchronous Enable"]
313    #[inline(always)]
314    pub fn prsasync(&mut self) -> PRSASYNC_W {
315        PRSASYNC_W::new(self)
316    }
317    #[doc = "Bits 12:14 - Channel 1 PRS Trigger Select"]
318    #[inline(always)]
319    pub fn prssel(&mut self) -> PRSSEL_W {
320        PRSSEL_W::new(self)
321    }
322    #[doc = "Writes raw bits to the register."]
323    #[inline(always)]
324    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
325        self.0.bits(bits);
326        self
327    }
328}
329#[doc = "Channel 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch1ctrl](index.html) module"]
330pub struct CH1CTRL_SPEC;
331impl crate::RegisterSpec for CH1CTRL_SPEC {
332    type Ux = u32;
333}
334#[doc = "`read()` method returns [ch1ctrl::R](R) reader structure"]
335impl crate::Readable for CH1CTRL_SPEC {
336    type Reader = R;
337}
338#[doc = "`write(|w| ..)` method takes [ch1ctrl::W](W) writer structure"]
339impl crate::Writable for CH1CTRL_SPEC {
340    type Writer = W;
341}
342#[doc = "`reset()` method sets CH1CTRL to value 0"]
343impl crate::Resettable for CH1CTRL_SPEC {
344    #[inline(always)]
345    fn reset_value() -> Self::Ux {
346        0
347    }
348}
efm32tg11b520_pac/vdac0/ch1ctrl.rs

efm32tg11b520_pac/vdac0/
ch1ctrl.rs
