efm32tg11b340_pac/cmu/
dpllctrl.rs

1#[doc = "Register `DPLLCTRL` reader"]
2pub struct R(crate::R<DPLLCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DPLLCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DPLLCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DPLLCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DPLLCTRL` writer"]
17pub struct W(crate::W<DPLLCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DPLLCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DPLLCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DPLLCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MODE` reader - Operating Mode Control"]
38pub type MODE_R = crate::BitReader<bool>;
39#[doc = "Field `MODE` writer - Operating Mode Control"]
40pub type MODE_W<'a> = crate::BitWriter<'a, u32, DPLLCTRL_SPEC, bool, 0>;
41#[doc = "Field `EDGESEL` reader - Reference Edge Select"]
42pub type EDGESEL_R = crate::BitReader<bool>;
43#[doc = "Field `EDGESEL` writer - Reference Edge Select"]
44pub type EDGESEL_W<'a> = crate::BitWriter<'a, u32, DPLLCTRL_SPEC, bool, 1>;
45#[doc = "Field `AUTORECOVER` reader - Automatic Recovery Ctrl"]
46pub type AUTORECOVER_R = crate::BitReader<bool>;
47#[doc = "Field `AUTORECOVER` writer - Automatic Recovery Ctrl"]
48pub type AUTORECOVER_W<'a> = crate::BitWriter<'a, u32, DPLLCTRL_SPEC, bool, 2>;
49#[doc = "Reference Clock Selection Control\n\nValue on reset: 0"]
50#[derive(Clone, Copy, Debug, PartialEq)]
51#[repr(u8)]
52pub enum REFSEL_A {
53    #[doc = "0: HFXO selected"]
54    HFXO = 0,
55    #[doc = "1: LFXO selected"]
56    LFXO = 1,
57    #[doc = "3: CLKIN0 selected"]
58    CLKIN0 = 3,
59}
60impl From<REFSEL_A> for u8 {
61    #[inline(always)]
62    fn from(variant: REFSEL_A) -> Self {
63        variant as _
64    }
65}
66#[doc = "Field `REFSEL` reader - Reference Clock Selection Control"]
67pub type REFSEL_R = crate::FieldReader<u8, REFSEL_A>;
68impl REFSEL_R {
69    #[doc = "Get enumerated values variant"]
70    #[inline(always)]
71    pub fn variant(&self) -> Option<REFSEL_A> {
72        match self.bits {
73            0 => Some(REFSEL_A::HFXO),
74            1 => Some(REFSEL_A::LFXO),
75            3 => Some(REFSEL_A::CLKIN0),
76            _ => None,
77        }
78    }
79    #[doc = "Checks if the value of the field is `HFXO`"]
80    #[inline(always)]
81    pub fn is_hfxo(&self) -> bool {
82        *self == REFSEL_A::HFXO
83    }
84    #[doc = "Checks if the value of the field is `LFXO`"]
85    #[inline(always)]
86    pub fn is_lfxo(&self) -> bool {
87        *self == REFSEL_A::LFXO
88    }
89    #[doc = "Checks if the value of the field is `CLKIN0`"]
90    #[inline(always)]
91    pub fn is_clkin0(&self) -> bool {
92        *self == REFSEL_A::CLKIN0
93    }
94}
95#[doc = "Field `REFSEL` writer - Reference Clock Selection Control"]
96pub type REFSEL_W<'a> = crate::FieldWriter<'a, u32, DPLLCTRL_SPEC, u8, REFSEL_A, 2, 3>;
97impl<'a> REFSEL_W<'a> {
98    #[doc = "HFXO selected"]
99    #[inline(always)]
100    pub fn hfxo(self) -> &'a mut W {
101        self.variant(REFSEL_A::HFXO)
102    }
103    #[doc = "LFXO selected"]
104    #[inline(always)]
105    pub fn lfxo(self) -> &'a mut W {
106        self.variant(REFSEL_A::LFXO)
107    }
108    #[doc = "CLKIN0 selected"]
109    #[inline(always)]
110    pub fn clkin0(self) -> &'a mut W {
111        self.variant(REFSEL_A::CLKIN0)
112    }
113}
114#[doc = "Field `DITHEN` reader - Dither Enable Control"]
115pub type DITHEN_R = crate::BitReader<bool>;
116#[doc = "Field `DITHEN` writer - Dither Enable Control"]
117pub type DITHEN_W<'a> = crate::BitWriter<'a, u32, DPLLCTRL_SPEC, bool, 6>;
118impl R {
119    #[doc = "Bit 0 - Operating Mode Control"]
120    #[inline(always)]
121    pub fn mode(&self) -> MODE_R {
122        MODE_R::new((self.bits & 1) != 0)
123    }
124    #[doc = "Bit 1 - Reference Edge Select"]
125    #[inline(always)]
126    pub fn edgesel(&self) -> EDGESEL_R {
127        EDGESEL_R::new(((self.bits >> 1) & 1) != 0)
128    }
129    #[doc = "Bit 2 - Automatic Recovery Ctrl"]
130    #[inline(always)]
131    pub fn autorecover(&self) -> AUTORECOVER_R {
132        AUTORECOVER_R::new(((self.bits >> 2) & 1) != 0)
133    }
134    #[doc = "Bits 3:4 - Reference Clock Selection Control"]
135    #[inline(always)]
136    pub fn refsel(&self) -> REFSEL_R {
137        REFSEL_R::new(((self.bits >> 3) & 3) as u8)
138    }
139    #[doc = "Bit 6 - Dither Enable Control"]
140    #[inline(always)]
141    pub fn dithen(&self) -> DITHEN_R {
142        DITHEN_R::new(((self.bits >> 6) & 1) != 0)
143    }
144}
145impl W {
146    #[doc = "Bit 0 - Operating Mode Control"]
147    #[inline(always)]
148    pub fn mode(&mut self) -> MODE_W {
149        MODE_W::new(self)
150    }
151    #[doc = "Bit 1 - Reference Edge Select"]
152    #[inline(always)]
153    pub fn edgesel(&mut self) -> EDGESEL_W {
154        EDGESEL_W::new(self)
155    }
156    #[doc = "Bit 2 - Automatic Recovery Ctrl"]
157    #[inline(always)]
158    pub fn autorecover(&mut self) -> AUTORECOVER_W {
159        AUTORECOVER_W::new(self)
160    }
161    #[doc = "Bits 3:4 - Reference Clock Selection Control"]
162    #[inline(always)]
163    pub fn refsel(&mut self) -> REFSEL_W {
164        REFSEL_W::new(self)
165    }
166    #[doc = "Bit 6 - Dither Enable Control"]
167    #[inline(always)]
168    pub fn dithen(&mut self) -> DITHEN_W {
169        DITHEN_W::new(self)
170    }
171    #[doc = "Writes raw bits to the register."]
172    #[inline(always)]
173    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
174        self.0.bits(bits);
175        self
176    }
177}
178#[doc = "DPLL Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrl](index.html) module"]
179pub struct DPLLCTRL_SPEC;
180impl crate::RegisterSpec for DPLLCTRL_SPEC {
181    type Ux = u32;
182}
183#[doc = "`read()` method returns [dpllctrl::R](R) reader structure"]
184impl crate::Readable for DPLLCTRL_SPEC {
185    type Reader = R;
186}
187#[doc = "`write(|w| ..)` method takes [dpllctrl::W](W) writer structure"]
188impl crate::Writable for DPLLCTRL_SPEC {
189    type Writer = W;
190}
191#[doc = "`reset()` method sets DPLLCTRL to value 0"]
192impl crate::Resettable for DPLLCTRL_SPEC {
193    #[inline(always)]
194    fn reset_value() -> Self::Ux {
195        0
196    }
197}
efm32tg11b340_pac/cmu/dpllctrl.rs

efm32tg11b340_pac/cmu/
dpllctrl.rs
